Trends in Low-Power RAM Circuit Technologies

Proceedings of the IEEE

Volumn 83, Issue 4, 1995, Pages 524-543

  Itoh, Kiyoo ^a   Nakagome, Yoshinobu ^a   Sasaki, Katsuro ^b  

^a HITACHI LTD   (Japan)

^b HITACHI AMERICA LTD   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; RANDOM ACCESS STORAGE;

ADDRESS TRANSITION DETECTION; AUTO POWER DOWN SCHEME; DATA LINE LOAD; DYNAMIC RANDOM ACCESS MEMORIES; LOW POWER CIRCUIT TECHNOLOGY; POWER REDUCTION; STATIC RANDOM ACCESS MEMORIES;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0029288557     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/5.371965     Document Type: Article

References (67)

1. K. Itoh, “Trends in megabit DRAM circuit design,” IEEE J. Solid-State Circ., vol. 25, pp. 778-789, June 1990.
2. Y. Nakagome and K. Itoh, “Review and prospects of DRAM technology,” IEICE Trans. Electron., vol. E74-C, no. 4, pp. 799-811, Apr. 1991.
3. Y. Nakagome et al., “An experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circ., vol. 26, pp. 465-472, Apr. 1991.
4. K. Satoh et al., “A 4 Mb pseudo-SRAM operating at 2.6 ± 1 V with 3 μA data-retention current,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 268-269.
5. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
6. M. Takada et al., “Reviews and prospects of SRAM technology,” IEICE Trans., vol. E74, no. 4, pp. 827-838, Apr. 1991.
7. K. Sasaki, “High-speed, low-voltage design for high-performance static RAM's,” in Proc. Tech. Papers, VLSI Tech., Syst., and Appl., May 1993, pp. 292-296.
8. M. Matsumiya et al., “A 15 ns 16Mb CMOS SRAM with reduced voltage amplitude data bus,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 214-215.
9. K. Kimura et al., “Power reduction techniques in megabit DRAM's,” IEEE J. Solid-State Circ., vol. SC-21, pp. 381-389, June 1986.
10. M. Aoki and K. Itoh, “Low-voltage, low-power ULSI circuit techniques,” IEICE Trans. Electron., vol. E77-c, no. 8, pp. 1351-1360, Aug. 1994.
11. K. Sasaki et al., “A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current,” IEEE J. Solid-State Circ., vol. 25, pp. 1075-1081, Oct. 1990.
12. S. Hayakawa et al., “A 1 μA retention 4 Mb SRAM with a thin-film-transistor load cell,” in ISSCC Dig. Tech. Papers, Feb. 1990, pp. 128-129.
13. K. Itoh et al., “An experimental 1 Mb DRAM with on-chip voltage limiter,” in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 106-107.
14. T. Sugibayashi et al., “A 30 ns 256 Mb DRAM with multi-divided array structure,” in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 50-51.
15. K. Fujishima et al., “A 256K dynamic RAM with page-nibble mode,” IEEE J. Solid-State Circ., vol. SC-18, pp. 470-478, Oct. 1983.
16. K. Itoh, “Reviews and prospects of deep sub-micron DRAM technology,” in Int. Conf. Solid-State Devices and Materials, Yokohama, Extended Abs., Aug. 1991, pp. 468-471.
17. K. Kenmizaki et al., “A 36 μA 4 Mb PSRAM with quadruple array operation,” in Symp. VLSI Circ. Dig. Tech. Papers, May 1989, pp. 79-80.
18. N. C. C. Lu and H. Chao, “Half-VDD bit-line sensing scheme in CMOS DRAM,” IEEE J. Solid-State Circ., vol. SC-19, pp. 451-454, Aug. 1984.
19. H. Kawamoto et al., “A 288-K CMOS pseudostatic RAM,” IEEE J. Solid-State Circ., vol. SC-19, pp. 619-623, Oct. 1984.
20. H. Tanaka et al., “Stabilization of voltage limiter circuit for high-density DRAM's using pole-zero compensation,” IEICE Trans. Electron., vol. E75-C, no. 11, pp. 1333-1343, Nov. 1992.
21. D. Chin et al., “An experimental 16-Mbit DRAM with reduced peak-current noise,” IEEE J. Solid-State Circ., vol. 24, pp. 1191-1197, June 1989.
22. R. S. Mao et al., “A new on-chip voltage regulator for high density CMOS DRAM's,” in Symp. VLSI Circ. Dig. Tech. Papers, June 1992, pp. 108-109.
23. M. Horiguchi et al., “Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test,” IEEE J. Solid-State Circ., vol. 26, no. 11, pp. 1544-1549, Nov. 1991.
24. Y. Nakagome et al., “The impact of data-line interference noise on DRAM scaling,” IEEE J. Solid-State Circ., vol. 23, pp. 1120-1127, Oct. 1988.
25. T. Yoshihara et al., “A twisted bit line technique for multi-Mb DRAM's,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 238-239.
26. N. C. C. Lu, “Advanced cell structures for dynamic RAM,” IEEE Circ. and Devices Mag., pp. 27-36, Jan. 1989.
27. T. Ema et al., “3-dimensional stacked capacitor cell for 16M and 64M DRAM's,” in IEDM Tech. Dig., Dec. 1988, pp. 592-595.
28. T. Horikawa et al., “(Ba0.75Sr0.25)TiO3 films for 256 Mbit DRAM,” IEICE Trans. Electron., vol. E77-C, no. 3, pp. 385-391, Mar. 1994.
29. K. Satoh et al., “A 20 ns static column 1 Mb DRAM in CMOS technology,” in ISSCC Dig. Tech. Papers, Feb. 1985, pp. 254-255.
30. G. Kitsukawa et al., “A 23-ns 1-Mb BiCMOS DRAM,” IEEE J. Solid-State Circ., vol. 25, pp. 1102-1111, Oct. 1990.
31. D. Lee et al., “A 35 ns 64 Mb DRAM using on-chip boosted power supply,” in Symp. on VLSI Circ. Dig. Tech. Papers, June 1992, pp. 64-65.
32. Y. Konishi et al., “A 38 ns 4 Mb DRAM with a battery back-up mode,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 230-231.
33. H. Tanaka et al., “Sub-1-μA dynamic reference voltage generator for battery-operated DRAM's,” in Symp. VLSI Circ. Dig. Tech. Papers, May 1993, pp. 87-88.
34. D. C. Choi et al., “Battery operated 16M DRAM with post package programmable and variable self refresh,” in Symp. VLSI Circ. Dig. Tech. Papers, June 1994, pp. 83-84.
35. K. Sawada et al., “Self-aligned refresh scheme for VLSI intelligent dynamic RAM's,” in Symp. VLSI Tech. Dig. Tech. Papers, May 1986, pp. 85-86.
36. M. Tsukude et al., “Automatic voltage-swing reduction (AVR) scheme for ultra low power DRAM's,” in Symp. VLSI Circ. Dig. Tech. Papers, June 1994, pp. 87-88.
37. T. Kawahara et al., “A charge recycle refresh for Gb-scale DRAM's in file applications,” in Symp. VLSI Circ. Dig. Tech. Papers, May 1993, pp. 41-42.
38. T. Sakata et al., “Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's,” in ESSCIRC Dig. Tech. Papers, Sept. 1993, pp. 33-36.
39. M. Horiguchi et al., “Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's,” IEEE J. Solid-State Circ., vol. 28, pp. 1131-1135, Nov. 1993.
40. T. Sakata et al., “Subthreshold-current reduction circuits for multi-gigabit DRAM's,” in Symp. VLSI Circ. Dig. Tech. Papers, May 1993, pp. 45-46.
41. G. Kitsukawa et al., “256 Mb DRAM technologies for file applications,” in ISSCC Dig. Tech. Papers, pp. 48-49, Feb. 1993.
42. T. Kawahara et al., “Subthreshold current reduction for decoded-driver by self biasing,” IEEE J. Solid-State Circ., vol. 28, pp. 1136-1144, Nov. 1993.
43. M. Asakura et al., “A 34 ns 256 Mb DRAM with boosted sense-ground scheme,” in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 140-141.
44. O. Minato et al., “A 42 ns 1 Mb CMOS SRAM,” in ISSCC Dig. Tech. Papers, Feb. 1987, pp. 260-261.
45. M. Yoshimoto et al., “A 64 Kb CMOS RAM with divided word line structure,” in ISSCC Dig. Tech. Papers, pp. 58-59, Feb. 1983.
46. F. Miyaji et al., “A 25 ns 4 Mb CMOS SRAM with dynamic bit line loads,” in ISSCC Dig. Tech. Papers, pp. 58-60, Feb. 1983.
47. T. Hirose et al., “A 20-ns 4-Mb CMOS RAM with hierarchical word decoding architecture,” IEEE J. Solid-State Circ., vol. 25, pp. 1068-1074, Oct. 1990.
48. O. Minato et al., “A 20 ns 64K CMOS RAM,” in ISSCC Dig. Tech. Papers, pp. 222-223, Feb. 1984.
49. T. Tsujide et al., “A 25 ns 16 × 1 static RAM,” in ISSCC Dig. Tech. Papers, pp. 20-21, Feb. 1981.
50. K. Hardee et al., “A fault-tolerant 30 ns/375 mW 16K × 1 NMOS static RAM,” IEEE J. Solid-State Circ., vol. SC-16, pp. 435-443, Oct. 1981.
51. S. Yamamoto et al., “A 256K CMOS RAM with variable-impedance loads,” in ISSCC Dig. Tech. Papers, pp. 58-59, Feb. 1985.
52. Y. Kobayashi et al., “A 10 μW standby-power 256K CMOS SRAM,” in ISSCC Dig. Tech. Papers, Feb. 1985, pp. 60-61.
53. S. Murakami et al., “A 21 mW 4 Mb CMOS SRAM for battery operation,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 46-47.
54. K. Sasaki et al., “A 15 ns 1 Mb CMOS RAM,” in ISSCC Dig. Tech. Papers, pp. 174-175, Feb. 1988.
55. K. Sasaki et al., “A 9-ns 1-Mbit CMOS RAM,” IEEE J. Solid-State Circ., vol. 24, pp. 1219-1225, Oct. 1989.
56. K. Ishibashi et al., “A 1 V TFT-load SRAM using a two-step word-voltage method,” IEEE J. Solid-State Circ., vol. 27, pp. 1519-1524, Nov. 1992.
57. K. Sasaki et al., “A 16 Mb CMOS SRAM with a 2.3 μm2 single-bit-line memory cell,” in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 250-251.
58. E. Seevinck, “A current sense-amplifier for fast CMOS SRAM,” in Symp. VLSI Circ. Dig. Tech. Papers, May 1990, pp. 71-72.
59. K. Sasaki et al., “A 7 ns 140 mW/Mb CMOS SRAM with current sense amplifier,” in ISSCC Dig. Tech. Papers,Feb. 1992, pp. 208-209.
60. A. Roberts et al., “A 256K SRAM with on-chip power supply conversion,” in ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 1987.
61. K. Ishibashi et al., “A voltage down converter with submicroampare standby current for low-power static RAM's,” IEEE J. Solid-State Circ., vol. 27, pp. 920-926, June 1992.
62. T. Yabe et al., “High-speed and low-standby-power circuit design of 1-5 V operating 1 Mb full CMOS SRAM,” in Symp. VLSI Circ. Dig. Tech. Papers, May 1993, pp. 107-108.
63. K. Ishibashi et al., “A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers,” in Symp. VLSI Circ. Dig. Tech. Papers, June 1994, pp. 107-108.
64. D. Burnett et al., “Implication of fundamental threshold voltage variations for high-density SRAM and logic circuits,” in Symp. VLSI Tech. Dig. Tech. Papers, May 1994, pp. 15-16.
65. S. Sun et al., “Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation,” in CICC Proc., May 1994, pp. 267-270.
66. K. Seno et al., “A 9 ns 16 Mb CMOS SRAM with offset reduced current sense amplifier,” in ISSCC Dig. Tech. Papers, pp. 248-249, Feb. 1993.
67. S. Flannagan et al., “Two 13-ns 64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques,” IEEE J. Solid-State Circ., vol. 21, pp. 692-703, Oct. 1986.