Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 25-26

  Mizuno, Hiroyuki ^a   Nagano, Takahiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGING (BATTERIES); COMPUTER ARCHITECTURE; ENERGY DISSIPATION; MOSFET DEVICES; RANDOM ACCESS STORAGE;

BIT-LINE SWING; CELL ARCHITECTURE; CELL LAYOUT PATTERN; CELL-ACCESS TIME; DRIVING SOURCE-LINE; HIGH-SPEED LOW-POWER APPLICATIONS; STATIC NOISE MARGIN;

LOGIC DESIGN;

EID: 0029513481     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)