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Volumn , Issue , 1996, Pages 33-38
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Wiring rule methodology for on-chip interconnects
a a
a
IBM
(United States)
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
CMOS INTEGRATED CIRCUITS;
DATABASE SYSTEMS;
ELECTRIC WIRING;
MICROPROCESSOR CHIPS;
OPTIMIZATION;
SPURIOUS SIGNAL NOISE;
ON CHIP INTERCONNECTS;
SIGNAL COUPLING;
SLEW RATE;
WIRING RULE METHODOLOGY;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0030388691
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (2)
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References (4)
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