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Volumn E76-C, Issue 11, 1993, Pages 1641-1648
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High-performance memory macrocells with row and column sliceable architecture
a
a
NTT CORPORATION
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
CELLULAR ARRAYS;
CMOS INTEGRATED CIRCUITS;
COMPUTER AIDED DESIGN;
DECODING;
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUIT MANUFACTURE;
PRODUCT DESIGN;
RANDOM ACCESS STORAGE;
ROM;
TURNAROUND TIME;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
HIGH PERFORMANCE MEMORY MACROCELLS;
ROW AND COLUMN SLICEABLE ARCHITECTURE;
SHORT DESIGN;
SEMICONDUCTOR STORAGE;
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EID: 0027698221
PISSN: 09168524
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
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Times cited : (15)
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References (6)
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