Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits

IEEE Transactions on Nuclear Science

Volumn 41, Issue 6, 1994, Pages 2229-2234

  Velazco, R ^a   Bessot, D ^a   Duzellier, S ^b   Ecoffet, R ^c   Koga, R ^d  

^a Laboratoire de Génie Informatique   (France)

^b ONERA   (France)

^c CNES   (France)

^d AEROSPACE CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CELLULAR ARRAYS; FAULT TOLERANT COMPUTER SYSTEMS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; IONS; LOGIC GATES; RADIATION EFFECTS; SEMICONDUCTING SILICON; SHIFT REGISTERS; TRANSISTORS; VLSI CIRCUITS;

CMOS MEMORY CELLS; HEAVY ION TOLERANT CELLS; RADIATION HARDENING; SINGLE EVENT UPSET;

CMOS INTEGRATED CIRCUITS;

EID: 0028727191     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.340567     Document Type: Article

References (9)

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8. D. Bessot, “Conception de deux points mémoire statiques CMOS durcis contre l'effet des aléas logiques provoqués par l'environnement radiatif spatial”, Doctoral dissertation INPG; 26 November 1993.
9. S. Duzellier, D. Falguère, “SEETEST tester: A test system dedicated to the S.E.E. characterization of memories”, 1st European Conference on Radiation Effects on Devices and Systems, RADECS, La Grande Motte, (France), September 1991.