Dynamic algorithm transformations (DAT) - A systematic approach to low-power reconfigurable signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 4, 1999, Pages 463-476

  Goel, Manish ^b   Shanbhag, Naresh R ^a,b  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Algorithm transformations; Low power; Reconfigurable computing; Signal processing

Indexed keywords

DYNAMIC ALGORITHM TRANSFORMATIONS (DAT); NEAR-END CROSSTALK (NEXT) CANCELLER; RECONFIGURABLE COMPUTING;

ALGORITHMS; COMPUTER SIMULATION; CROSSTALK; ERROR ANALYSIS; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; SIGNAL TO NOISE RATIO; STATE SPACE METHODS;

DIGITAL SIGNAL PROCESSING;

EID: 0033280649     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.805753     Document Type: Article

References (42)

1. A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen, "Minimizing power using transformations," IEEE Trans. Computer-Aided Design, vol. 14, pp. 12-31, Jan. 1995.
2. D. A. Parker and K. K. Parhi, "Low-area/power parallel FIR digital filter implementations," J. VLSI Signal Processing, vol. 17, pp. 75-92, Sept. 1997.
3. N. R. Shanbhag and M. Goel, "Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN," IEEE Trans. Signal Processing, vol. 45, no. 5, pp. 1276-1290, May 1997.
4. E. Tsern and T. H. Meng, "A low-power videorate pyramid VQ decoder," IEEE J. Solid-State Circuits, vol. 31, pp. 1789-1794, Nov. 1996.
5. H. H. Loomis and B. Sinha, "High speed recursive digital filter realization," Circuit, Syst., Signal Processing, vol. 3, no. 3, pp. 267-294, 1984.
6. K. K. Parhi and D. G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters - Part I & II," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1099-1134, July 1989.
7. A. Shen, A. Ghosh, S. Devdas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in IEEE Int. Conf. Computer-Aided Design, 1992, pp. 402-407.
8. S. Iman and M. Pedram, "An approach for multilevel logic optimization targeting low-power," IEEE Trans. Computer-Aided Design, vol. 15, pp. 889-901, Aug. 1996.
9. M. Alidina, J. Monterio, S. Devdas, A. Ghosh, and M. Papaefthymiou, "Precomputation-based sequence logic optimization for low-power," IEEE Trans. VLSI Syst., vol. 2, pp. 398-407, Dec. 1994.
10. Y. Nakagome et al., "Sub-1 V swing internal bus architecture for future low-power ULSI's," IEEE J. Solid-State Circuits, vol. 28, pp. 414-419, Apr. 1993.
11. W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y.-C. Chou, "Low-power digital systems based on adiabatic switching principles," IEEE Trans. VLSI Syst., vol. 2, pp. 398-407, Dec. 1994.
12. B. Davan, R. H. Dennard, and G. G. Shahidi, "CMOS scaling for high-performance and low-power - The next ten years," Proc. IEEE, vol. 83, pp. 595-606, Apr. 1995.
13. K. K. Parhi, "Algorithm transformation techniques for concurrent processors," Proc. IEEE, vol. 77, pp. 1879-1895, Dec. 1989.
14. N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Norwell, MA: Kluwer, 1994.
15. M. Potkonjak and J. Rabaey, "Fast implementation of recursive programs using transformations," in Proc. ICASSP, San Francisco, CA, Mar. 1992, pp. 569-572.
16. C. Leiserson and J. Saxe, "Optimizing synchronous systems," J. VLSI Comput. Syst., vol. 1, pp. 41-67, 1983.
17. A. Abnous and J. M. Rabaey, "Ultra-low-power domain-specific multimedia processors," in Proc. IEEE VLSI Signal Processing Workshop, Oct. 1996, pp. 461-470.
18. J. T. Ludwig, S. H. Nawab, and A. P. Chandrakasan, "Low-power digital filtering using approximate processing," IEEE J. Solid-State Circuits, vol. 31, pp. 395-400, Mar. 1996.
19. V. Gutnik and A. P. Chandrakasan, "Embedded power supply for low-power DSP," IEEE Trans. VLSI Syst., vol. 12, pp. 425-435, Dec. 1997.
20. D. Keppel, "A portable interface for on-the-fly instruction space modification," in Proc. 4th Int. Conf. ASPLOS-IV, Apr. 1991, pp. 86-95.
21. C. Consel and F. Noël, "A general approach for run-time specialization and application to C," in Proc. 23rd ACM SIGPLAN-SIGACT Symp. POPL, Jan. 1996, pp. 145-156.
22. J. Villasenor and B. Hutchings, "The flexibility of configurable computing," IEEE Signal Processing Mag., pp. 67-84, Sept. 1998.
23. S. Trimberger, D. Carberry, A. Johnson, and J. Wong, "A time-multiplexed FPGA," in Proc. IEEE Workshop FPGA's Custom Comput. Machines, J. Arnold and K. L. Pocek, Eds., Napa, CA, Apr. 1997, pp. 22-28.
24. N. Shirazi, P. M. Athanas, and A. L. Abbott, "Implementation of a 2-D fast Fourier transform on an FPGA - Based custom computing machine," in Field-Programmable Logic Applicat. 5th Int. Workshop Field-Programmable Logic Applicat., W. Moore and W. Luk, Eds., Oxford, U.K., Sept. 1995, pp. 282-292.
25. J. R. Hauser and J. Wawrzynek, "GARP: A MIPS processor with a reconfigurable coprocessor," in Proc. IEEE Workshop FPGA's Custom Comput. Machines, J. Arnold and K. L. Pocek, Eds., Napa, CA, Apr. 1997, pp. 12-21.
26. C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale, "The NAPA adaptive processing architecture," in IEEE Symp. Field-Programmable Custom Comput. Machines, Napa, CA, Apr. 1998, pp. 23-37.
27. M. Goel and N. R. Shanbhag, "Low-power equalizers for 51.84 Mb/s very high-speed digital subscriber loop (VDSL) modems," in IEEE Workshop Signal Processing Syst.: Design and Implementation, Boston, MA, Oct. 1998, pp. 317-326.
28. _, "Dynamic algorithm transformations (DAT) for low-power adaptive signal processing," in Int. Symp. Low-Power Electron, and Design, Monterey, CA, Aug. 1997, pp. 161-166.
29. S. Haykin, Adaptive Filter Theory. Englewood Cliff, NJ: Prentice-Hall, 1991.
30. B. Widrow et al., "Stationary and nonstationary learning characteristics of the LMS adaptive filter," Proc. IEEE, vol. 64, pp. 1151-1162, Aug. 1976.
31. V. Gutnik, "Variable supply voltage for low power DSP," Master's thesis, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, May 1996.
32. R. E. Gonzalez, "Low-power processor design," Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Stanford Univ., Stanford, CA, June 1997.
33. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1988.
34. N. Sankarayya, K. Roy, and D. Bhattacharya, "Algorithms for low power and high speed fir filter realization using differential coefficients," IEEE Trans. Circuits Syst. II, vol. 44, pp. 488-497, June 1997.
35. M. G. Xakellis and F. N. Najm, "Statistical estimation of the switching activity in digital circuits," in Design Automation Conf., June 1994, pp. 728-733.
36. C. J. Nicol, P. Larsson, K. Azadet, and J. H. O'Neill, "A low power 128-tap digital adaptive equalizer for broadband modems," IEEE J. Solid-State Circuits, vol. 32, pp. 1777-1789, Nov. 1997.
37. D. P. Bertsekas, Nonlinear Programming. Boston, MA: Athena Scientific, 1995.
38. M. Goel and N. R. Shanbhag, "Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers," IEEE Trans. Signal Processing, to be published.
39. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1994.
40. G. H. Im and J. J. Werner, "Bandwidth-efficient digital transmission up to 155-Mb/s over unshielded twisted-pair wiring," IEEE J. Select. Areas Commun., vol. 13, pp. 1643-1655, Dec. 1995.
41. 155.52 Mb/s Physical Layer Specifications for Category 3 Unshielded Twisted Pair, ATM Forum Tech. Committee af-phy-0047.00, Nov. 1995.
42. Commercial Building Telecommunications Cabling Standard, Standard TIA/EIA-568-A, 1994.