Design of ADPLL for both large lock-in range and good tracking performance

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 9, 1999, Pages 1192-1204

  Kim, Nam Guk ^a   Ha, In Joong ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONIC CIRCUIT TRACKING; ESTIMATION; NUMERICAL ANALYSIS; OSCILLATORS (ELECTRONIC);

ALL DIGITAL PHASE LOCKED LOOPS; FREQUENCY OFFSET ESTIMATOR; LARGE LOCK-IN RANGE; PHASE ERROR ESTIMATION;

PHASE LOCKED LOOPS;

EID: 0033189238     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.793709     Document Type: Article

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