A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 2, 1991, Pages 116-121

  Miyazawa, Shyoichi ^a   Horita, Ryutaro ^a   Hase, Kenichi ^a   Kato, Kazuo ^a   Kojima, Shinichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, MAGNETIC--HARD DISK; INTEGRATED CIRCUITS, HYBRID; PHASE LOCKED LOOPS;

ANALOG PHASE LOCKED LOOP; BICMOS TECHNOLOGY; DATA SEPARATOR CIRCUIT; DIGITAL SYNCHRONIZATION FIELD DETECTOR; WINCHESTER DISK DRIVE;

INTEGRATED CIRCUITS, CMOS;

EID: 0026103756     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.68125     Document Type: Article

References (4)

1. J. T. Kellis and S. Mehrozra, “A 15-Mb/s data separator and write compensation circuit for Winchester disk drives,” in ISSCC Dig, Tech. Papers, Feb. 1986, pp. 232–233.
2. K. Kato et. al., “A low power dissipation PLL IC operating at 128 MHz clock,” in IEEE 1987 CICC Conf. Rec., May 1987, pp. 651–654.
3. R. W. Wood, “Magnetic recording systems,” Proc. IEEE, vol. 74, no. 11, pp. 1557–1569, Nov. 1986.
4. “Data synchronizer/2, 7 RLL ENDEC with write precompensation SSI 32D535,” product manual, Silicon Systems.