A 155-MHz Clock Recovery Delay- and Phase-Locked Loop

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 12, 1992, Pages 1736-1746

  Bulzacchelli, John F ^b  

^a RAMBUS INC   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL OSCILLATORS; DELAY CIRCUITS; MONOLITHIC INTEGRATED CIRCUITS; OPTICAL COMMUNICATION EQUIPMENT; PHASE LOCKED LOOPS; TRANSFER FUNCTIONS;

CLOCK RECOVERY; DELAY-LOCKED LOOP; JITTER TRANSFER FUNCTION; PHASE DETECTORS;

SIGNAL RECEIVERS;

EID: 0026996358     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.173100     Document Type: Article

References (6)

1. J. Bulzacchelli, U.S. Patent 5 036 298, July 1991.
2. P. Trischitta and E. Varma, Jitter in Digital Transmission Systems. Dedham, MA: Artech House, 1989.
3. L. DeVito et al., “A 52MHz and 155MHz clock-recovery PLL,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 142–143.
4. C. R. Hogge, “A self-correcting clock recovery circuit,” J. Lightwave Technol., vol. LT-3, no. 6, pp. 1312–1314, 1985.
5. J. Bulzacchelli, “A delay-locked loop forlock recovery and data synchronization,” Master's thesis, Massachusetts Inst, of Technology, Cambridge, June 1990.
6. T. H. Lee and J. F. Bulzacchelli, “A 155MHz clock recovery delay-and phase-locked loop,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 160–161.