A High Lock-In Speed Digital Phase-Locked Loop

IEEE Transactions on Communications

Volumn 39, Issue 3, 1991, Pages 365-368

  Hao, Shi ^a   Puqiang, Yan ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FILTERS; ELECTRONIC CIRCUITS, FREQUENCY MULTIPLYING; MATHEMATICAL TRANSFORMATIONS - Z TRANSFORMS; SIGNAL PROCESSING - DIGITAL TECHNIQUES; SPEECH - ANALYSIS;

DIGITAL FREQUENCY MULTIPLIER; DIGITAL PHASE LOCKED LOOP; PHASE COMPARATOR; PHASE DETECTOR; PITCH SYNCHRONOUS ANALYSIS;

PHASE LOCKED LOOPS;

EID: 0026117448     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.79274     Document Type: Note

References (6)

1. L. R. Rabiner and R. W. Schafer, Digital Processing of Speech Signals. Englewood Cliffs, NJ: Prentice-Hall, 1978.
2. S. Hao, “Chinese speech recognition for controlling of man-machine system,” Master's thesis, Tsinghua Univ., 1985.
3. M. C. Lindsey and C. M. Chie, “A survey of digital phase-locked loops,” Proc. IEEE, vol. 69, 1981.
4. F. Michele, “Circuit increase frequency to 1000,” EDN, Oct. 3, 1985.
5. S. Hao and Y. Puqiang, “Complete period analysis of voiced sounds,” J. Acoust. Soc. Amer., vol. 86, no. 3, pp. 1172–1175, 1989.
6. S. Hao, “Complete period analysis of voiced sound and its recognition by process parameters,” Ph.D. dissertation, Tsinghua Univ., 1988.