ILLIADS: A Fast Timing and Reliability Simulator for Digital MOS Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 9, 1993, Pages 1387-1402

  Shih, Yung Ho ^a   Leblebici, Yusef ^b   Kang, Sung Mo ^c  

^a MICROSOFT   (United States)

^b ISTANBUL TECHNICAL UNIVERSITY   (Turkey)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; RELIABILITY; SIMULATION;

FAST TIMING SIMULATOR; ILLIADS;

CMOS INTEGRATED CIRCUITS;

EID: 0027664687     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.240086     Document Type: Article

References (28)

1. B. Chawla, H. Gummel, and P. Kozak, “MOTIS—an MOS timing simulator,” IEEE Trans. Circuits Syst., vol. CAS-22, pp. 901–910, Dec. 1975.
2. C. Chen and P. Subramaniam, “The second generation MOTIS timing simulator—an efficient and accurate approach for general MOS circuits,” in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 538–542, May 1984.
3. V. B. Rao, T. N. Trick, and I. N. Hajj, “A table-driven delay-operator approach to timing simulation of MOS VLSI circuits,” in Proc. IEEE Int. Conf. on Computer Design, New York, pp. 445–448, Nov. 1983.
4. V. B. Rao, ''Switch-Level Timing Simulation of MOS VLSI Circuits,” Ph.D. dissertation, Dep. Elec. Comp. Eng. Univ. of Illinois, Urbana, IL, 1985.
5. F.P. Lai, V. B. Rao, and T. N. Trick, “JADE: A hierarchical switch level timing simulator,” in Proc. IEEE Int. Symp. on Circuits and Systems, Philadelphia, pp. 592–595, May 1987.
6. H. N. Nham and A. K. Bose, ''A multiple delay simulator for MOS LSI circuits,” in Proc. 17th Design Automation Conf., pp. 610–617, June 1980.
7. T. Tokuda, K. Okazaki, K. Sakashita, I. Ohkura, and T. Enomoto, “Delay-time modeling for ED MOS logic, LSI,” IEEE Trans. Computer-Aided Design, CAD-2 pp. 129–134, July 1983.
8. Y. H. Jun and S. B. Park, “An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1027–1032, Sept. 1989.
9. D. Overhauser, I. N. Hajj, and V. B. Rao, “Switch-level timing analysis of VLSI MOS circuits including parasitics,” in Proc. IEEE Int. Symp. on Circuits and Systems, Santa Jose, CA, pp. 761–764, May 1986.
10. D. Overhauser and I. N. Hajj, “A tubular macromodeling approach to fast timing simulation including parasitics,” in Proc. IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1988.
11. Y.H. Shih and S. M. Kang, “Analytic transient solution of general MOS circuit primitives,” IEEE Tarns. Computer-Aided Design, vol. 11, pp. 719–731, June 1992.
12. S. Aur, D. Hocevar, and P. Yang, “HOTRON—a circuit hot electron effect simulator,” in Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 256–259, Nov. 1987.
13. Y. Leblebici and S. M. Kang, “An integrated reliability simulation tool for hot-carrier resistant VLSI design,” in Proc. of TECHCON Conf., pp. 102–105, Oct. 1990.
14. Y. Leblebici and S. M. Kang, “An integrated hot-carrier degradation simulator for VLSI reliability analysis,” in Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 400–403, Nov. 1990.
15. Y. Leblebici, P. C. Li, S. M. Kang, and 1. N. Hajj, “Hierarchical simulation of hot-carrier induced damages in VLSI circuits,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 29.3.1-29.3.4, May 1991.
16. H. Shichman and D. A. Hodges, “Modeling and simulation of insulated gate field effect transistor switching circuits,” IEEE J. Solid-State Circuits, SC-3, pp. 245–259, Sept. 1968.
17. Carl E. Pearson, Handbook of Applied Mathematics Princeton, NJ: Van Nostrand Reinhold Company, 1974, ch. 6.
18. Y. H. Chang and A. T. Yang, “Analytic macromodeling and simulation of strongly coupled mixed analog-digital circuits,” in Proc. IEEE Int. Conf on Computer-Aided Design, Santa Clara, CA, Nov. 1992, pp. 244–247.
19. M. Shoji. CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice-Hall, 1987, ch.3.
20. S. R. Vemuru and A. R. Thorbjomsen, “A model for delay evaluation of a CMOS inverter’’ in Proc. IEEE Int. Symp. on Circuits and Systems, New Orleans pp. 89–92, May 1990.
21. E. Acuna, J. P. Dervenis, A. J. Pagones, F. L. Yang, and R. A. Saleh, “Simulation techniques for mixed analog/digital circuits,” IEEE J. of Solid-State Circuits, vol. 25, 353–363, Apr. 1990.
22. D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits. New York: McGraw-Hill Book Company, 1983.
23. R. E. Tarjan, “Depth first search and linear graph algorithms,” SIAM J. Computing, vol. 1, no. 2 pp. 146–160, 1972.
24. C. Hu, S. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terril, “Hot-electron-induced MOSFET degradation—model, monitor and improvement,” IEEE Trans. Electron Devices, ED-32, pp. 375–384, Feb. 1985.
25. M. M. Kuo, K. Seki, P. M. Lee, J. Y. Choi, P. K. Ko, and C. Hu, “Simulation of MOSFET lifetime under AC hot-electron stress,” IEEE Trans. Electron Devices, ED-35, pp. 1004–1011, July 1988.
26. A. T. Yang and S. M. Kang, “A novel circuit simulation program with emphasis on new device model development,” in Proc. ACM/ IEEE Design Automation Conf., pp. 630–633, June 1989.
27. B. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, “Interface state creation and charge trapping in the medium-to-high gate voltage range (v d/2 < v g < v d) during hot-carrier stressing of n MOS transistors,” IEEE Trans. Electron Devices, vol. 37, pp. 744–754, Mar. 1990.
28. Y. Leblebici and S. M. Kang, “Modeling of nMOS transistor for simulation of hot-carrier induced device and circuit degradation,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 235–246, Feb. 1992.