Direct synthesis of hazard-free asynchronous circuits from STGs based on lock relation and MG-decomposition approach

Proceedings of the European Design and Test Conference

Volumn , Issue , 1994, Pages 178-183

  Lin, Kuan Jen ^a   Kuo, Jih Wen ^a   Lin, Chen Shang ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; HAZARDS AND RACE CONDITIONS; MINIMIZATION OF SWITCHING NETS; PETRI NETS; POLYNOMIALS; STATE ASSIGNMENT;

BOOLEAN MINIMIZATION; DIRECT SYNTHESIS ALGORITHMS; FREE CHOICE PETRI NETS; HAZARD FREE ASYNCHRONOUS CIRCUITS; REALIZABILITY; SIGNAL LOCK RELATION; SIGNAL TRANSITION GRAPHS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0028018595     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)