Automatic synthesis of gate-level timed circuits with choice

Proceedings - 16th Conference on Advanced Research in VLSI, ARVLSI 1995

Volumn , Issue , 1995, Pages 42-58

  Myers, C J ^a   Rokicki, T G ^a,b   Meng, T H Y ^a  

^a STANFORD UNIVERSITY   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; SPECIFICATIONS; VLSI CIRCUITS;

ASYNCHRONOUS CIRCUITS; AUTOMATIC SYNTHESIS; CIRCUIT COMPLEXITY; DESIGN METHODOLOGY; GENERAL SPECIFICATION; GRAPHICAL REPRESENTATIONS; SYNTHESIS PROCEDURE; TIMING INFORMATION;

TIMING CIRCUITS;

EID: 33749897712     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1995.515610     Document Type: Conference Paper

References (21)

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