Automatic Synthesis of Asynchronous Circuits from High-Level Specifications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 8, Issue 11, 1989, Pages 1185-1205

  Meng, Teresa H Y ^a   Brodersen, Robert W ^b   Messerschmitt, David G ^b  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER PROGRAMMING--ALGORITHMS; MATHEMATICAL TECHNIQUES--GRAPH THEORY;

ASYNCHRONOUS CIRCUITS; INTERCONNECTED CIRCUITS; SIGNAL TRANSITION GRAPHS;

LOGIC CIRCUITS;

EID: 0024771230     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.41504     Document Type: Article

References (70)

1. S. Y. Kung and R. J. Gal-Ezer, “Synchronous versus asynchronous computation in very large scale integration array processors,” SPIE, Real Time Signal Processing V, p. 341, 1982.
2. M. Hatamian and G. L. Cash, “Parallel bit-level pipelined VLSI designs for highspeed signal processing,” Proc. IEEE, vol. 75, pp. 1192-1202, Sept. 1987.
3. D. F. Wann and M. A. Franklin, “Asynchronous and clocked control structures for VLSI based interconnection network,” IEEE Trans. Comput., vol. C-32, Mar. 1983.
4. G. Jacobs and R. W. Brodersen, “Self-timed integrated circuits for digital signal processing applications,” VLSI Signal Processing III. New York: IEEE Press, Nov. 1988.
5. T. H.-Y. Meng, G. W. Jacobs, R. W. Brodersen, and D. G. Messerschmitt,” “Asynchronous processor design for digital signal processing,” in Proc. IEEE ICASSP 1988, Apr. 1988.
6. T. H.-Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, “Implementation of high sampling rate adaptive filters using asynchronous design techniques,” VLSI Signal Processing III. New York: IEEE Press, Nov. 1988.
7. W. A. Clark, “Macromodular computer systems,” in Proc. 1967 Spring Joint Computer Conf., pp. 335-336, 1967.
8. R. J. Swan, S. H. Fuller, and D. P. Siewiorek, “CM*-A modular multiprocessor,” in Proc. AFIPS 1977Nat. Computer Conf., pp. 637644, 1977.
9. D. A. Huffman, “The synthesis of sequential switching circuits,” J. Franklin Instit., vol. 257, pp. 161-190; 275-203, Mar./Apr. 1954.
10. R. E. Miller, Switching Theory. New York: Wiley, 1965.
11. Gyula Mago, “Realization methods for asynchronous sequential circuits,” IEEE Trans. Comput., vol. C-20, Mar. 1971.
12. S. H. Unger, “Asynchronous sequential switching circuits with unrestricted input changes,” IEEE Trans. Comput., vol. C-20, pp. 1437-1444, Dec. 1971.
13. Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience.
14. D. B. Armstrong, A. D. Friedman, and P. R. Manon, “Design of asynchronous circuits assuming unbounded gate delays,” IEEE Trans. Comput., vol. C-18, Dec. 1969.
15. A. S. Wojcik and K.-Y. Fang, “On the design of three-valued asynchronous modules,” IEEE Trans. Comput., vol. C-29, Oct. 1980.
16. J. C. Jr. Sims and H. J. Gray, “Design criteria for autoasynchronous circuits,” in Proc. Eastern Joint Computer Conf, pp. 94-99, Dec. 1958.
17. D. E. Muller, “Asynchronous logics and applications to information processing,” in Proc. Symp. Applications Switching Theory Space Technology, pp. 289-297, 1963.
18. D. Hammel, “Ideas on asynchronous feedback networks,” in Proc. 5th Ann. Symp. Switching Circuit Theory Logic Design, pp. 4-11, Nov. 1964.
19. G. R. Couranz and D. F. Wann, “Theoretical and experimental behavior of synchronizers operating in the metastable region,” IEEE Trans. Comput., vol. C-24, June 1975.
20. W. Plummer, “Asynchronous arbiters,” IEEE Trans. Comput., vol. C-21, Jan. 1972.
21. D. Kinniment and J. Woods, “Synchronization and arbitration circuits in digital systems,” in Proc. Inst. Elec. Eng., vol. 123, no. 10, 1976.
22. J. Calvo, J. I. Acha, and M. Valencia, “Asynchronous modular arbiter,” IEEE Trans. Comput., vol. C-35, Jan. 1986.
23. J. C. Barros and B. W. Johnson, “Equivalence of the arbiter, the synchronizer, the latch, and the inertial delay,” IEEE Trans. Comput., vol. C-32, July 1983.
24. J. Hohl, W. Larsen, and L. Schooley, “Prediction of error probability for integrated digital synchronizers,” IEEE J. Solid-State Circuits, vol. SC-19, 1982.
25. D. L. Dill and E. M. Clarke, “Automatic verification of asynchronous circuits using temporal logic,” in Proc. 1985 Chapel Hill Conf. Very Large Scale Integration, pp. 127-143, 1985.
26. T. E. Williams, M. Horowitz, R. L. Alverson, and T. S. Yang, “A self-timed chip for division,” in Advanced Research in VLSI, Proc. 1987 Stanford Conf, pp. 75-96, Mar. 1987.
27. S. E. Schuster et al., “A 15ns CMOS 64K RAM,” in Proc. 1SSCC 1986, pp. 206-207, Feb. 1986.
28. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, chap. 7, 1980.
29. D. M. Chapiro, “Globally-asynchronous locally-synchronous systems,” Ph.D. dissertation, Stanford Univ., Oct. 1986.
30. S. Y. Kung, K. S. Arun, R. J. Gal-Ezer, and D. V. BhaskarRao, “Wavefront array processor: Language, architecture, and applications,” IEEE Trans. Comput., vol. C-31, p. 1054, Nov. 1982.
31. T. H.-Y. Meng, R. W. Brodersen, andD. G. Messerschmitt, “Asynchronous logic synthesis for signal processing from high level specifications,” IEEE ICCAD'87 Dig. Technical Papers, Nov. 1987.
32. C. L. Seitz, “Self-timed VLSI systems,” in Proc. Cal Tech Conf. VLSI, Jan. 1979.
33. D. E. Muller, “Infinite sequences and finite machines,” in Proc. 4th Ann. IEEE Symp. Switching Circuit Theory Logical Design, vol. S-156, pp. 9-16, Sept. 1963.
34. L. G. Heller and W. R. Griffin, “Cascode voltage switch logic: A differential CMOS logic family,” in 1984 IEEE ISSCC Dig. Technical Papers, Feb. 1984.
35. R. K. Brayton and C. McMullen, “Decomposition and factorization of Boolean expressions,” in Proc. IEEE ICAS, May 1982.
36. C. K. Erdelyi, W. R. Griffin, and R. D. Kilmoyer, “Cascode voltage switch logic design,” VLSI Design, Oct. 1984.
37. E. W. Dijkstra, “Guarded commands, nondeterminacy and formal derivation of programs,” Comm. Ass. Comput. Math., vol. 18, no. 8, pp. 453-457, Aug. 1975.
38. T. A. Chu, “Synthesis of self-times control circuits from graphs: An example,” in Proc. IEEE 1986 1CCD, pp. 565-571, Oct. 1986.
39. F. Commoner and A. W. Holt, “Marked directed graphs,” J. Comput. Syst. Sci., vol. 5, pp. 511-523, 1971.
40. T. H.-Y. Meng, “Asynchronous design for digital signal processing architectures,” Ph.D. dissertation EECS Dep. Univ. Calif., Berkeley, 1988.
41. D. E. Muller and W. S. Barsky, “A theory of asynchronous circuits,” in Proc. Int. Symp. Theory Switching, pp. 204-243, 1959.
42. D. B. Gillies, “Flow chart notation for the description of a speed independent control,” in Proc. 2nd Ann. IEEE Symp. Switching Circuit Theory Logical Design, vol. S-134, Oct. 1961.
43. R. E. Swartwout, “One method for designing speed independent logic for a control,” in Proc. 2nd Ann. IEEE Symp. Switching Circuit Theory Logical Design, vol. S-134, Oct. 1961.
44. “New techniques for designing speed independent control logic,” in Proc. 5th Ann. IEEE Symp. Switching Circuit Theory Logical Design, vol. S-164, Nov. 1964.
45. J. van de Snepscheut, “Trace theory and VLSI design,” in Lecture Notes on Computer Science 200. Berlin, F.R.G.: Springer-Verlag, 1985.
46. T. Agerwala, “Putting Petri nets to work,” IEEE Comp., pp. 85-94, Dec. 1979.
47. D. Misunas, “Petri nets and speed independent design,” Comm. Ass. Comput. Math., vol. 16, no. 8, pp. 474-481, Aug. 1973.
48. J. B. Dennis, “Modular, asynchronous control structure for a high performance processor,” in Rec. Project MAC Conf. Concurrent Parallel Computation, ACM, pp. 55-80, 1970.
49. S. S. Patil and J. B. Dennis, “The description and realization of digital systems,” in IEEE COMPCON '72, Dig. Papers, pp. 223-226, 1972.
50. C. W. Rose and M. Albarran, “Modeling and design description of hierarchical hardware/software systems,” in Proc. 12th Design Automation Conf, pp. 421-430, June 1975.
51. P. Azema, etal., “Petri Nets as a common tool for design verification and hardware simulation,” in Proc. 13 th Design Automation Conf, pp. 109-116, June 1976.
52. P. M. Merlin, “A methodology for the design and implementation of communcation protocols,” IEEE Trans. Commun., vol. COM-24, pp. 614-621, June 1976.
53. J. L. Peterson, “Petri Nets,” Computing Surveys, vol. 9, no. 3, pp. 221-252, Sept. 1977.
54. R. M. Keller, “Towards a theory of universal speed-independent modules,” IEEE Trans. Comput., vol. C-23, pp. 21-33, Jan. 1974.
55. T. M. Carter, “ASSANSSIN: An assembly, specification and analysis system for speed independent control-unit design in integrated circuits using PPL,” Master's Thesis, Dep. Comput. Sci., Univ. Utah, June 1982.
56. A. J. Martin, “The design of a self-timed circuit for distributed mutual exclusion,” in Proc. 1985 Chapel Hill Conf. Very Large Scale Integration, pp. 245-283, 1985.
57. M. Hack, “Analysis of production schemata by Petri nets,” MAC TR-94, Project MAC, MIT, Feb. 1972.
58. E. B. Eichelberger, “Hazard detection in combinational and sequential switching circuits,” IBM J., Mar. 1965.
59. C. A. R. Hoare, “Communicating squential processes,” Comm. Ass. Comput. Math., vol. 21, no. 8, pp. 666-677, Aug. 1978.
60. R. L. Brayton, R. L. Rudell, A. Sagiovanni-Vincentelli, and A. R. Wang, “MIS: A Multilevel logic optimization system,” IEEE Trans. Computer-Aided Design, vol. CAD-6, Nov. 1987.
61. R. L. Rudell and K. J. Singh, WOLFE User's Manual, Berkeley CAD Tools, Apr. 1988.
62. A. J. Martin, “Compiling communicating processes into delay-insensitive VLSI circuits,” Distributed Computing, vol. 1, pp. 226-234, 1986.
63. S. Bums, private communications. May 1988.
64. A. J. Martin, private communications, May 1988.
65. C. Berthet and E. Cemy, “An algebraic model for asynchronous circuits verifications,” Trans. Comput., vol. 37, pp. 835-847, July 1988.
66. R. L. Rudell and A. Sangiovanni-Vincentelli, “Multiple-valued minimization for PLA optimization,” IEEE Trans. Computer-Aided Design, vol. CAD-6, Sept. 1987.
67. T. A. Chu, “A method of abstraction for petri nets,” presented at Int. Workshop Petri Nets Performance Models, Aug. 1987.
68. T. H.-Y. Meng. R. W. Brodersen, and D. G. Messerschmitt, “Asynchronous design for programmable digital signal processors,” to be published.
69. A. R. Newton, “Timing, logic, and mixed-mode simulation for large MOS integrated circuits,” in Computer Design Aids for VLSI Circuit. The Hague, The Netherlands: Matinus Nijhoff, 1984, pp. 175-240.
70. S. A. Szygenda and E. W. Thompson, “Modeling and digital simulation for design verification and diagnosis,” IEEE Trans. Comput., vol. C-25, pp. 1242-1253, Dec. 1976.