New VLSI array processor design for image window operations

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 5, 1999, Pages 635-640

  Li, D J ^a   Jiang, L ^a   Isshiki, T ^a   Kunieda, H ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; SYSTOLIC ARRAYS; VLSI CIRCUITS;

WINDOW-MEMORY SHARING PROCESSOR ARRAY;

MICROPROCESSOR CHIPS;

EID: 0032625191     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.769813     Document Type: Article

References (13)

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