메뉴 건너뛰기




Volumn E79-A, Issue 12, 1996, Pages 2097-2105

Automatic synthesis of a serial input multiprocessor array

Author keywords

Data path synthesis; Multiplier; Processor array; Serial interface

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); LOGIC GATES; MULTIPLYING CIRCUITS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

EID: 0030400505     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (4)

References (9)
  • 1
    • 33746382987 scopus 로고
    • Effective processor array architecture with shared memory
    • H. Kunieda and K. Hagiwara, "Effective processor array architecture with shared memory," IEEE, APCCAS'94, pp.113-118, 1994.
    • (1994) IEEE, APCCAS'94 , pp. 113-118
    • Kunieda, H.1    Hagiwara, K.2
  • 4
    • 0030106788 scopus 로고    scopus 로고
    • Optimal synthesis of algorithm-specific lower-dimensional processor arrays
    • IEEE, June
    • K. Ganapathy and B.W. Wah, "Optimal synthesis of algorithm-specific lower-dimensional processor arrays," IEEE Trans. Parallel and Distributed System, IEEE, vol.7, no.4, pp.274-287, June 1996.
    • (1996) IEEE Trans. Parallel and Distributed System , vol.7 , Issue.4 , pp. 274-287
    • Ganapathy, K.1    Wah, B.W.2
  • 5
    • 0026897642 scopus 로고
    • Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation
    • K.K. Parhi, "Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation," IEEE Trans. Circuits & Syst.-II: Analog and Digital Signal Processing, vol.39, no.7, pp.423-440, 1992.
    • (1992) IEEE Trans. Circuits & Syst.-II: Analog and Digital Signal Processing , vol.39 , Issue.7 , pp. 423-440
    • Parhi, K.K.1
  • 6
    • 0016945783 scopus 로고
    • Two's complement pipeline multipliers
    • April
    • R.E. Lyon, "Two's complement pipeline multipliers," IEEE Trans. Commun., vol.COM-24, pp.418-425, April 1976.
    • (1976) IEEE Trans. Commun. , vol.COM-24 , pp. 418-425
    • Lyon, R.E.1
  • 7
    • 0023648830 scopus 로고
    • Serial/parallel auto-multiplier
    • S.G. Smith, "Serial/parallel auto-multiplier," Electron. Letters, vol.23, no.8, pp.413-415, 1987.
    • (1987) Electron. Letters , vol.23 , Issue.8 , pp. 413-415
    • Smith, S.G.1
  • 8
    • 0026822192 scopus 로고
    • High-performance bit-serial adders and multipliers
    • Feb.
    • B. Bi and E.B. Jones, "High-performance bit-serial adders and multipliers," IEEE Proc. Circuits, Devices and Systems, vol.139, no.1, pp.109-113, Feb. 1992.
    • (1992) IEEE Proc. Circuits, Devices and Systems , vol.139 , Issue.1 , pp. 109-113
    • Bi, B.1    Jones, E.B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.