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Volumn E79-A, Issue 12, 1996, Pages 2086-2096

Memory sharing processor array (MSPA) architecture

Author keywords

Data path synthesis; Processor array; Systolic array

Indexed keywords

ALGORITHMS; DATA STORAGE EQUIPMENT; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SYSTOLIC ARRAYS;

EID: 0030394597     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (7)

References (9)
  • 1
    • 0024126651 scopus 로고
    • Time optimal linear schedules for algorithms with uniform dependencies
    • May
    • W. Shang and J.A.B. Fortes, "Time optimal linear schedules for algorithms with uniform dependencies," International Conference on SYSTOLIC ARRAYS, pp.393-402, May 1988.
    • (1988) International Conference on SYSTOLIC ARRAYS , pp. 393-402
    • Shang, W.1    Fortes, J.A.B.2
  • 2
    • 0026897642 scopus 로고
    • Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation
    • K.K. Parhi, "Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation," IEEE Trans. Circuits & Syst.-II: Analog and Digital Signal Processing, vol.39, no.7, pp.423-440, 1992.
    • (1992) IEEE Trans. Circuits & Syst.-II: Analog and Digital Signal Processing , vol.39 , Issue.7 , pp. 423-440
    • Parhi, K.K.1
  • 4
    • 0020207178 scopus 로고
    • On the analysis and synthesis of VLSI algorithms
    • Nov.
    • D.I. Moldovan, "On the analysis and synthesis of VLSI algorithms," IEEE Trans. Comput., vol.C-31, pp.1121-1126, Nov. 1982.
    • (1982) IEEE Trans. Comput. , vol.C-31 , pp. 1121-1126
    • Moldovan, D.I.1
  • 5
    • 0030106788 scopus 로고    scopus 로고
    • Optimal synthesis of algorithm-specific lower-dimensional processor arrays
    • June
    • K. Ganapathy and B.W. Wah, "Optimal synthesis of algorithm-specific lower-dimensional processor arrays," IEEE Trans. Parallel and Distributed System, vol.7, no.4, pp.274-287, June 1996.
    • (1996) IEEE Trans. Parallel and Distributed System , vol.7 , Issue.4 , pp. 274-287
    • Ganapathy, K.1    Wah, B.W.2
  • 6
    • 33746382987 scopus 로고
    • Effective processor array architecture with shared memory
    • H. Kunieda and K. Hagiwara, "Effective processor array architecture with shared memory," IEEE, APCCAS'94, pp.113-118, 1994.
    • (1994) IEEE, APCCAS'94 , pp. 113-118
    • Kunieda, H.1    Hagiwara, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.