VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1994, Pages 124-129

  Delgado Frias, Jose G ^a   Sze, Rovy ^a   Summerville, Douglas H ^a   Aiknes, Valentine ^a  

^a BINGHAMTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT PATTERN MATCHING; CONTENT ADDRESSABLE MEMORY; DETERMINISTIC COMMUNICATION PATH; FLEXIBLE OBLIVIOUS ROUTER; INTERCONNECTION NETWORK TOPOLOGIES; MULTIPROCESSOR INTERCONNECTION NETWORKS; OBLIVIOUS ROUTING ALGORITHMS; PARALLEL INTERCONNECTION NETWORK ARCHITECTURE;

ALGORITHMS; COMPUTER AIDED MANUFACTURING; DATA STORAGE EQUIPMENT; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

DATA COMMUNICATION EQUIPMENT;

EID: 0028748662     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)