The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI

IEEE Transactions on Computers

Volumn C-30, Issue 4, 1981, Pages 247-253

  Zorat, Alessandro ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b STONY BROOK UNIVERSITY   (United States)

Author keywords

Binary trees; multiprocessing; networks; parallelism; VLSI

Indexed keywords

INTEGRATED CIRCUITS - VERY LARGE SCALE INTEGRATION;

COMPUTER SYSTEMS, DIGITAL;

EID: 0019007733     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1981.1675772     Document Type: Article

References (10)

1. J. Backus, “Can programming be liberated from the von Neumann style? A functional style and its algebra of programs,” Commun. Ass. Comput. Mach., vol. 21, pp. 613–641, Aug. 1978.
2. J. Bentley and H. T. Kung, “A tree machine for searching problems,” in Proc. IEEE 1979 Int. Conf. Parallel Processing, Bellaire, MI, Aug. 1979.
3. A. Despain and D. Patterson, “X-tree: A structured multiprocessor computer architecture,” in Proc. IEEE 5th Annu. Symp. Comput. Arch., Apr. 1978, pp. 144–151.
4. J. Harris and D. Smith, “Simulation experiments of a tree organized multicomputer,” in Proc. IEEE 6th Annu. Symp. Comput. Arch., Apr. 1979, pp. 83–89.
5. E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms. Potomac, MD: Science Press, 1978.
6. E. Horowitz and A. Zorat, “A divide and conquer computer,” Dep. Comput. Sci., Univ. of Southern California, Tech. Rep., July 1979.
7. C. E. Leiserson, “Systolic priority queues,” in Proc. Caltech Conf. on VLSI, Jan. 1979, pp. 199–214.
8. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
9. M. Rem, “Mathematical aspects of VLSI design,” in Proc. Caltech Conf. on VLSI, Jan. 1979, pp. 55–63.
10. C. Sequin, “Single chip computers, the new VLSI building blocks,” in Proc. Caltech Conf. on VLSI, Jan. 1979, pp. 435–446.