Dynamic Cross-Coupled Bit-Line Content Addressable Memory Cell for High-Density Arrays

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 1, 1987, Pages 119-121

  Wade, Jon P ^a   Sodini, Charles G ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR - COMPUTER AIDED DESIGN;

CONTENT ADDRESSABLE MEMORY; DYNAMIC CROSS-COUPLING; HIGH DENSITY ARRAYS;

DATA STORAGE UNITS;

EID: 0023291701     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052684     Document Type: Article

References (6)

1. C. G. Sodini et al., “The MIT database accelerator: A novel content addressable memory,” In Proc. Wescon, 1986.
2. D. Crandall, “A content addressable memory,” Univ. of Calif., Berkley, Res. Project, Apr. 1981.
3. H. Kodata, J. Miyake, Y. Nishimichi, H. Kudo, and K. Kagawa, “An 8Kb content-addressable and reentrant memory,” in ISSCC Dig. Tech. Papers, vol. 18, 1985, pp. 42–43.
4. J. L. Mundy, “High density four-transistor MOS content addressable memory,” U.S. Patent 3 701 980, Oct. 31, 1972.
5. J. L. Mundy, J. F. Burgess, R. E. Joynston, and C. Neugebauer, “Low-cost associative memory,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 364–369, Oct. 1972.
6. W. D. Jansen and D. G. Fairbairn, “The silicon foundry: Concepts and reality,” Lambda, vol. 2, no. 1, pp. 16–25, Jan. 1981.