Optimal burn-in decision making

Quality and Reliability Engineering International

Volumn 14, Issue 6 SPEC. ISS. 1, 1998, Pages 417-423

  Kim, Taeho ^a   Kuo, Way ^a,b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b Texas AandM University   (United States)

Author keywords

Burn in; Package level burn in; Semiconductor devices; Wafer level burn in

Indexed keywords

ELECTRONICS PACKAGING; FAILURE ANALYSIS; INTEGRATED CIRCUITS; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

BURN-IN; PACKAGE LEVEL BURN-IN; WAFER LEVEL BURN-IN;

DECISION MAKING;

EID: 0032202103     PISSN: 07488017     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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