120mm2 64Mb NAND flash memory achieving 180ns/byte effective program speed

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 168-169

  Kim, Jin Ki ^a   Sakui, Koji ^a   Lee, Sung Soo ^a   Itoh, Yasuo ^a   Kwon, Suk Chon ^a   Kanazawa, Kazuhisa ^a   Lee, Ki Jun ^a   Nakamura, Hiroshi ^a   Kim, Kang Young ^a   Himeno, Toshihiko ^a   Kim, Jang Rae ^a   Kanda, Kazushige ^a   Jung, Tae Sung ^a   Oshima, Yoichi ^a   Suh, Kang Deog ^a   et al , ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; ELECTRIC BREAKDOWN; NAND CIRCUITS; OSCILLATORS (ELECTRONIC); RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MANUFACTURE; TRANSISTORS;

CHARGE PUMPING CIRCUIT; CMOS TECHNOLOGY; INCREMENTAL STEP PULSE PROGRAMMING SCHEME; NAND FLASH MEMORY; NARROW INCREMENTAL STEP PULSE PROGRAMMING TECHNIQUE; RANDOM ACCESS TIME; STAGGERED ROW DECODER SCHEME;

NONVOLATILE STORAGE;

EID: 0029714787     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)