Synthesis of Control Circuits in Folded Pipelined DSP Architectures

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 1, 1992, Pages 29-43

  Parhi, Keshab K ^a   Wang, Ching Yi ^a   Brown, Andrew P ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b 3M COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS, DIGITAL - PIPELINE PROCESSING; COMPUTER SYSTEMS, DIGITAL - REAL TIME OPERATION; ELECTRIC FILTERS, DIGITAL; MATHEMATICAL TECHNIQUES - GRAPH THEORY;

AUTOMATED PIPELINING; DATA FLOW GRAPH FOLDING; FOLDED CIRCUITS; MULTIPLE CLOCKS; PIPELINED DSP ARCHITECTURES; SYSTEMATIC FOLDING TRANSFORMATION TECHNIQUE;

SIGNAL PROCESSING;

EID: 0026707183     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.109555     Document Type: Article

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