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1
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0024706222
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Algorithms for hardware allocation in data path synthesis
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Devadas, S.1
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Optimal synthesis of highperformance architectures
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C. H. Gebotys and M. I. Elmasry, “Optimal synthesis of highperformance architectures,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 389–397, 1992.
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IEEE J. Solid-State Circuits
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Gebotys, C.H.1
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3
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An algorithm for component selection in performance optimized scheduling
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Ramachandran, L.1
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Making use of timing constraints for controller synthesis
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R. Zahir and W. Fichtner, “Making use of timing constraints for controller synthesis,” presented at the Workshop on High Level Synthesis, 1989.
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Workshop on High Level Synthesis
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Zahir, R.1
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5
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Sehwa: A software package for synthesis of pipelines from behavioral specifications
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N. Park and A. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications,” IEEE Trans. Computer-Aided Design, vol. 7, no. 3, pp. 356–370, Mar. 1988.
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Park, N.1
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A formal method for the specification, analysis and design of register-transfer-level digital logic
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L. Hafer and A. Parker, “A formal method for the specification, analysis and design of register-transfer-level digital logic,” IEEE Trans. Computer-Aided Design, vol. CAD-2, no. 1, pp. 4–17, 1983.
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Hafer, L.1
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0026960523
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Optimal scheduling and allocation of embedded VLSI chips
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presented at the
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C. H. Gebotys, “Optimal scheduling and allocation of embedded VLSI chips,” presented at the ACM/IEEE, Design Automation Conf., 1992.
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ACM/IEEE, Design Automation Conf.
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Gebotys, C.H.1
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8
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Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits
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D. C. Ku and G. DeMicheli, “Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits,” IEEE Trans. Computer-Aided Design, vol. 11, no. 6, pp. 696–718, 1992.
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Ku, D.C.1
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Solving large scale zero-one linear programming problems
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H. Crowder, E. L. Johnson, and M. Padberg, “Solving large scale zero-one linear programming problems,” Operations Res., vol. 31, no. 5, pp. 803–834, 1983.
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Crowder, H.1
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0026139605
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A formal approach to the scheduling problem in high-level synthesis
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C-T Hwang, J-H. Lee, and Y-C. Hsu, “A formal approach to the scheduling problem in high-level synthesis,” IEEE Trans. Computer-Aided Design, vol. 10, no. 4, pp. 464–475, 1991.
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Hwang, C.-T.1
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0343051755
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Norwell, MA: Kluwer Academic
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C. H. Gebotys and M. I. Elmasry, Optimal VLSI Architectural Synthesis: Area, Performance, Testability. Norwell, MA: Kluwer Academic, 1992.
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Optimal VLSI Architectural Synthesis: Area, Performance, Testability
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Gebotys, C.H.1
Elmasry, M.I.2
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84870042796
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Synthesizing embedded speed-optimized architectures
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presented at the
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C. H. Gebotys, “Synthesizing embedded speed-optimized architectures,” presented at the IEEE Custom Integrated Circuits Conf., 1992.
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(1992)
IEEE Custom Integrated Circuits Conf.
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Gebotys, C.H.1
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15
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84941526118
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High-Level Synthesis-Benchmarks-Clearinghouse, Coordinator N. Dutt, dutt@ics.uci.edu., 1992.
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(1992)
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16
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Synthesis of application-specific multiprocessor architectures
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in
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Proc. Design Automation Conf.
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Prakash, S.1
Parker, A.C.2
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0026851981
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Combined hardware selection and pipelining in high performance data path design
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S. Note, F. Catthoor, G. Goossens, and H. DeMan, “Combined hardware selection and pipelining in high performance data path design,” IEEE Trans. Computer-Aided Design, vol. 11, no. 4, 413–423 1992.
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Note, S.1
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0026985090
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Optimal synthesis of multichip architectures
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presented at the
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C. H. Gebotys, “Optimal synthesis of multichip architectures,” presented at the IEEE Int. Conf. Computer Aided Design, 1992.
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(1992)
IEEE Int. Conf. Computer Aided Design
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Gebotys, C.H.1
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