메뉴 건너뛰기




Volumn 28, Issue 3, 1993, Pages 242-252

Synthesizing embedded speed-optimized architectures

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; MATHEMATICAL PROGRAMMING; OPTIMIZATION;

EID: 0027558825     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.209990     Document Type: Article
Times cited : (11)

References (19)
  • 1
    • 0024706222 scopus 로고
    • Algorithms for hardware allocation in data path synthesis
    • July
    • S. Devadas and A. R. Newton, “Algorithms for hardware allocation in data path synthesis,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 768–781, July 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.8 , pp. 768-781
    • Devadas, S.1    Newton, A.R.2
  • 2
    • 0026837903 scopus 로고
    • Optimal synthesis of highperformance architectures
    • C. H. Gebotys and M. I. Elmasry, “Optimal synthesis of highperformance architectures,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 389–397, 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.3 , pp. 389-397
    • Gebotys, C.H.1    Elmasry, M.I.2
  • 3
    • 0027098867 scopus 로고
    • An algorithm for component selection in performance optimized scheduling
    • in
    • L. Ramachandran and D. D. Gajski, “An algorithm for component selection in performance optimized scheduling,” in Proc. IEEE ICCAD, 1991, pp. 92–95.
    • (1991) Proc. IEEE ICCAD , pp. 92-95
    • Ramachandran, L.1    Gajski, D.D.2
  • 4
    • 84941504338 scopus 로고
    • Making use of timing constraints for controller synthesis
    • presented at the
    • R. Zahir and W. Fichtner, “Making use of timing constraints for controller synthesis,” presented at the Workshop on High Level Synthesis, 1989.
    • (1989) Workshop on High Level Synthesis
    • Zahir, R.1    Fichtner, W.2
  • 5
    • 0023983163 scopus 로고
    • Sehwa: A software package for synthesis of pipelines from behavioral specifications
    • Mar
    • N. Park and A. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications,” IEEE Trans. Computer-Aided Design, vol. 7, no. 3, pp. 356–370, Mar. 1988.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , Issue.3 , pp. 356-370
    • Park, N.1    Parker, A.2
  • 6
    • 0020544208 scopus 로고
    • A formal method for the specification, analysis and design of register-transfer-level digital logic
    • L. Hafer and A. Parker, “A formal method for the specification, analysis and design of register-transfer-level digital logic,” IEEE Trans. Computer-Aided Design, vol. CAD-2, no. 1, pp. 4–17, 1983.
    • (1983) IEEE Trans. Computer-Aided Design , vol.CAD-2 , Issue.1 , pp. 4-17
    • Hafer, L.1    Parker, A.2
  • 7
    • 0026960523 scopus 로고
    • Optimal scheduling and allocation of embedded VLSI chips
    • presented at the
    • C. H. Gebotys, “Optimal scheduling and allocation of embedded VLSI chips,” presented at the ACM/IEEE, Design Automation Conf., 1992.
    • (1992) ACM/IEEE, Design Automation Conf.
    • Gebotys, C.H.1
  • 8
    • 0026883812 scopus 로고
    • Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits
    • D. C. Ku and G. DeMicheli, “Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits,” IEEE Trans. Computer-Aided Design, vol. 11, no. 6, pp. 696–718, 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.11 , Issue.6 , pp. 696-718
    • Ku, D.C.1    DeMicheli, G.2
  • 11
    • 0020815626 scopus 로고
    • Solving large scale zero-one linear programming problems
    • H. Crowder, E. L. Johnson, and M. Padberg, “Solving large scale zero-one linear programming problems,” Operations Res., vol. 31, no. 5, pp. 803–834, 1983.
    • (1983) Operations Res. , vol.31 , Issue.5 , pp. 803-834
    • Crowder, H.1    Johnson, E.L.2    Padberg, M.3
  • 12
    • 0026139605 scopus 로고
    • A formal approach to the scheduling problem in high-level synthesis
    • C-T Hwang, J-H. Lee, and Y-C. Hsu, “A formal approach to the scheduling problem in high-level synthesis,” IEEE Trans. Computer-Aided Design, vol. 10, no. 4, pp. 464–475, 1991.
    • (1991) IEEE Trans. Computer-Aided Design , vol.10 , Issue.4 , pp. 464-475
    • Hwang, C.-T.1    Lee, J.-H.2    Hsu, Y.-C.3
  • 14
    • 84870042796 scopus 로고
    • Synthesizing embedded speed-optimized architectures
    • presented at the
    • C. H. Gebotys, “Synthesizing embedded speed-optimized architectures,” presented at the IEEE Custom Integrated Circuits Conf., 1992.
    • (1992) IEEE Custom Integrated Circuits Conf.
    • Gebotys, C.H.1
  • 15
    • 84941526118 scopus 로고
    • High-Level Synthesis-Benchmarks-Clearinghouse, Coordinator N. Dutt, dutt@ics.uci.edu., 1992.
    • (1992)
  • 16
    • 0026175224 scopus 로고
    • Synthesis of application-specific multiprocessor architectures
    • in
    • S. Prakash and A. C. Parker, “Synthesis of application-specific multiprocessor architectures,” in Proc. Design Automation Conf., 1991, pp. 8–13.
    • (1991) Proc. Design Automation Conf. , pp. 8-13
    • Prakash, S.1    Parker, A.C.2
  • 17
    • 0026851981 scopus 로고
    • Combined hardware selection and pipelining in high performance data path design
    • S. Note, F. Catthoor, G. Goossens, and H. DeMan, “Combined hardware selection and pipelining in high performance data path design,” IEEE Trans. Computer-Aided Design, vol. 11, no. 4, 413–423 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.11 , Issue.4 , pp. 413-423
    • Note, S.1    Catthoor, F.2    Goossens, G.3    DeMan, H.4
  • 19
    • 0026985090 scopus 로고
    • Optimal synthesis of multichip architectures
    • presented at the
    • C. H. Gebotys, “Optimal synthesis of multichip architectures,” presented at the IEEE Int. Conf. Computer Aided Design, 1992.
    • (1992) IEEE Int. Conf. Computer Aided Design
    • Gebotys, C.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.