Behavioral to Structural Translation in a Bit-Serial Silicon Compiler

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 8, 1988, Pages 877-886

  Hartley, Richard I ^a   Jasica, Jeffrey R ^a  

^a GE GLOBAL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY -- MANY VALUED LOGICS; COMPUTER PROGRAMMING -- ALGORITHMS; MATHEMATICAL PROGRAMMING, LINEAR;

BEHAVIORAL-TO-STRUCTURAL TRANSLATION; BIT-SERIAL LANGUAGE (BSL); BIT-SERIAL SILICON COMPILER; LOGICAL AND ARITHMETIC OPERATORS; SHORTEST PATH ALGORITHM;

INTEGRATED CIRCUITS;

EID: 0024055843     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3219     Document Type: Article

References (27)

1. Neil Bergman, “A Case Study of the FIRST Silicon Compiler”, Third Caltech Conference on VLSI, 1983.
2. Y. S. Cheung and S. C. Leung, “A second generation compiler for bit-serial signal processing architecture”, in Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, pp. 487-490, 1987.
3. Peter B. Denyer, “An Introduction to Bit-Serial Architectures for VLSI Signal Processing”, VLSI Architecture, Prentice-Hall International, 1982.
4. Peter Denyer and David Renshaw, VLSI Signal Processing: A Bit-Serial Approach. Reading, MA: Addison-Wesley, 1985.
5. Louis J. Hafer and Alice C. Parker, “Automated synthesis of digital hardware”, IEEE Trans. Computers, vol. C-31, pp. 93-109, Feb. 1982.
6. Paul N. Hilfinger, “A high-level language and silicon compiler for digital signal processing”, IEEE Custom Integrated Circuits Conf. Portland, OR, pp. 213-216, 1985.
7. Mary J. Irwin and Robert M. Owens, “Digit-pipelined arithmetic as illustrated by the paste-up system: A tutorial”, Computer, pp. 61-73, Apr. 1987.
8. Leland B. Jackson, James F. Kaiser, and Henry S. McDonald, “An approach to the implementation of digital filters”, IEEE Trans. Audio Electroacoust., vol. AU-16, pp. 413-421, Sept. 1968.
9. Rajeev Jain, et al. “Custom design of a VLSI PCM-FDM transmultiplexor from system specification to circuit layout using a computer-aided design system”, IEEE J. Solid-State Circuits, vol. SC-21, pp. 73-85, Feb. 1986.
10. Jeffrey R. Jasica, Richard Hartley, Sharbel Noujaim, and Michael Hartman, “A bit-serial silicon compiler”, in Proc. Int. Conf. Computer-Aided Design (ICCAD-85), Santa Clara, CA, pp. 91-93, 1985.
11. Donald E. Knuth, The Art of Computer Programming, vol. 1, Reading, MA: Addison-Wesley, (second edition) 1979, pp. 258-268.
12. T. J. Kowalski and D. E. Thomas, “The VLSI design automation assistant: Prototype system”, in Proc. 20th Design Automation Conf. pp. 479-483, June 1983.
13. C. E. Leiserson, F. M. Rose and J. B. Saxe, “Digital circuit optimization”, M.I.T. report, 1982.
14. C. E. Leiserson and J. B. Saxe, “Optimizing synchronous systems”, in Proc. 22nd Ann. Symp. on Foundations of Computer Science, 1981.
15. Richard F. Lyon, A Bit-Serial VLSI Architectural Methodology for Signal Processing, VLSI 81, New York: Academic, 1981.
16. Alan F. Murray, and Peter B. Denyer, “A CMOS design strategy for bit-serial signal processing”, IEEE J. Solid-State Circuits, vol. SC-20, June 1985.
17. Sharbel E. Noujaim, Richard I. Hartley, Harvey E. Cline, Ronald T. Jerdonek, and Siegwalt Ludke, “30 MHz compiled chip set for graphics computations”, in Proc. 30th Int. Solid State Circuits Conf. pp. 310-311, 441, Feb. 1987.
18. Robert M. Owens, and Mary J. Irwin, “Towards designing, testing, and validating high performance VLSI signal processors”, in Dig. Tech. Papers, ICCAD-85, Santa Clara, CA, Nov. 1985.
19. Jan M. Rabaey, Stephen P. Pope, and R. W. Brodersen, “An integrated automated layout generation system for DSP circuits”, IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 285-296, July 1985.
20. F. M. Rose, “Models for VLSI circuits”, MIT master's thesis, 1982.
21. Fathy Yassa, Jeffrey Jasica, Richard Hartley, and Sharbel Noujaim, “A silicon compiler for digital signal processing: Methodology, implementation and applications”, Proc. IEEE, vol. 75, Sept. 1987.
22. G. Zimmermann, “The MIMOLA design system: A computer aided digital processor design method”, Proc. 16th Design Automation Conf, pp. 53-58, June 1979.
23. R. Camposano and A. Kunzmann, “Considering timing constraints in synthesis from a behavioural description”, in Proc. Int. Conf. Computer Design (ICCD), 1986, pp. 6-9.
24. L. Claesen et al. “Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers”, to appear in Proc. Custom Integrated Circuits Conf, 1988.
25. G. Goosens, R. Jain, J. Vandewalle, and H. de Man, “An optimal and flexible delay management technique for VLSI”, in Proc. Int. Symp. Mathematical Theory of Networks and Systems (Stockholm), 1985.
26. S. C. Leung, and Y. S. Cheung, “Automatic time alignment computation”, University of Hong Kong tech. rep., 1987.
27. N. Park and A. Parker, “Sehwa : A software package for synthesis of pipelines from behavioral specifications”, IEEE Trans. Computer-Aided Design, vol. 7, pp. 356-370, Mar. 1988.