High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI:) SOI wafer

IEEE Transactions on Electron Devices

Volumn 45, Issue 5, 1998, Pages 1111-1115

  Horiuchi, Masatada ^a   Teshima, Tatsuya ^a   Tokumasu, Kazuya ^a   Yamaguchi, Ken ^a  

^a HITACHI LTD   (Japan)

Author keywords

Poly si; Punchthrough drain resistance; SOI MOSFET; Subthreshold turn off properties

Indexed keywords

CAPACITANCE; CRYSTAL IMPURITIES; DIFFUSION IN SOLIDS; ELECTRIC RESISTANCE; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SILICA; SILICON WAFERS; ULTRATHIN FILMS;

POLY SILICON INTERLAYERED (PSI); PUNCHTHROUGH DRAIN RESISTANCE; SUBTHRESHOLD TURN OFF PROPERTIES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0032075637     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.669551     Document Type: Article

References (10)

1. M. Yoshimi, M. Terauchi, A. Murakoshi, M. Takahashi, M. Matsuzawa, N. Shigyo, and Y. Ushiku, "Technology trends of silicon-oninsulator-Its advantages and problems to be solved," in IEDM Tech. Dig., 1994, p. 429.
2. T. Ohno, M. Takahashi, A. Ohtaka, Y. Sakakibara, and T. Tsuchiya, "Suppression of the parasitic bipolar effect in ultra-thin-film nMOSFET's/SIMOX by Ar ion implantation into source/drain regions," in IEDM Tech. Dig., 1995, p. 627.
3. M. Horiuchi and M. Tamura, "BESS: A source structure that fully suppresses the floating body effects in SOI CMOSFET's," in IEDM Tech. Dig., 1996, p. 121.
4. K. Yamaguchi, Y. Shiraki, Y. Katayama, and Y. Murayama, "A new short-channel MOSFET with an atomic-layer-doped impurity-profile, (ALD-MOSFET)," in Ext. Abst. SSDM, 1982, p. 91.
5. M. Horiuchi and K. Ohyu, "One-decade reduction of pn-junction leakage current using poly-Si interlayered SOI structures," in IEDM Tech. Dig., 1993, p. 847.
6. M. Horiuchi and S. Aoki, "Characteristics of silicon wafer-bond strengthening by annealing," J. Electrochem. Soc., 139, no. 9, p. 2589, 1992.
7. P. Mumola and G. Gardopee, "Advances in the production of thin-film bonded SOI and ultra flat bulk wafers using plasma assisted chemical etching," in Ext. Abst. SSDM, 1994, p. 256.
8. N. Lu, L. Gerzberg, C.-Y. Lu, and J. Meindl, "Modeling and optimization of monolithic polycrystalline silicon resistors," IEEE Trans. Electron Devices, ED-28, p. 818, 1981.
9. K. Yamaguchi, K. Tokumasu, T. Teshima, and M. Horiuchi, "Modeling and characterization of an SOI-MOSFET with an electrically floating interlayer," IEEE Trans. Electron Devices, to be published.
10. A. Auberton-Herve, "SOI; Materials to systems," in IEDM Tech. Dig., 1996, p. 3.