A Unified Approach to Floorplan Sizing and Enumeration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 12, 1993, Pages 1858-1867

  Yeap, Gary Kok Hoo ^a   Sarrafzadeh, Majid ^b  

^a MOTOROLA INC   (United States)

^b NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; OPTIMIZATION;

FLOORPLAN SIZING; RECTANGULAR DUAL;

INTEGRATED CIRCUIT LAYOUT;

EID: 0027809232     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.251149     Document Type: Article

References (26)

1. J. Bhasker and S. Sahni, “A linear algorithm to find a rectangular dual of a planar triangulated graph,” Algorithmica, vol. 3, no. 2, pp. 274–278, 1988.
2. J. D. Conway and G. G. Schrooten, “An automatic layout generator for analog circuits,” in Proc. Eur. Design Automation Conf., 1992, pp. 513–519.
3. M. R. Garey and D. S. Johnson, Computers and Intractability; A Guide to the Theory of NP-completeness. New York: Freeman, 1979.
4. R. Jayakumar, K. Thulasiraman, and M. N. S. Swamy, “O(n 2) algorithms for graph planarization,” IEEE Trans. Computer-Aided Design., vol. 8, pp. 257–267, 1989.
5. G. Kant, “An O(n 2) Maximal Planarization Algorithm based on PQ-trees,” Tech. Rep. RUU-CS-92-03, Dept. Comp. Sci., Utrecht Univ., The Netherlands, Jan. 1992.
6. K. Kozminski, “Benchmarks for layout synthesis—Evolution and current status,” in Proc. Design Automation Conf., 1991, pp. 265–270.
7. K. Kozminski and E. Kinnen, “Rectangular dual of planar graphs,” Networks, vol. 15, pp. 145–157, 1985.
8. K. Kozminski and E. Kinnen, “Rectangular dualization and rectangular dissection,” IEEE Trans. Circ. and Syst., vol. CS-35, pp. 1401–1416, 1988.
9. Y. T. Lai and S. M. Leinwand, “Algorithms for floor-plan design via rectangular dualization,” IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 1278–1289, Dec. 1988.
10. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. New York: Wiley, 1990.
11. R. H. J. M. Otten, “Automatic floorplan design,” in Proc. Design Automation Conf., 1982, pp. 261–267.
12. R. H. J. M. Otten, “Efficient floorplan optimization,” in Proc. Int. Conf. on Computer Design, 1983, pp. 499–503.
13. L. Stockmeyer, “Optimal orientation of cells in slicing floorplan designs,” Information and Control., vol. 57, no. 2, pp. 91–101, 1983.
14. Y. Sun and M. Sarrafzadeh, “Floorplanning by graph dualization: L-shaped models,” in Proc. Int. Symp. on Circuits and Systems, 1990, pp. 2845–2848.
15. S. Sur-Kolay and B. Bhattacharya, “On the family of inherently nonslicible floorplans in VLSI layout design,” in Proc. Int. Symp. on Circuits and Systems, 1991, pp. 2850–2853.
16. K. Tani, S. Tsukiyama, I. Shirakawa, and H. Ariyoshi, “Area-efficient drawings of rectangular duals for VLSI floorplan,” in Proc. Int. Symp. on Circuits and Systems, 1988, pp. 1545–1548.
17. S. Tsukiyama, K. Tani, and T. Maruyama, “A condition for a maximal planar graph to have a unique rectangular dual and its application to VLSI floor-plan,” in Proc. Int. Symp. on Circuits and Systems, 1989, pp. 931–934.
18. L. P. P. P. van Ginneken and R. H. J. M. Otten, “Optimal slicing of plane point placements,” in Proc. Eur. Design Automation Conf., 1990, pp. 322–326.
19. T. C. Wang and D. F. Wong, “A graph theoretic technique to speed up floorplan area optimization,” in Proc. Design Automation Conf., 1992, pp. 62–68.
20. T. C. Wang and D. F. Wong, “An optimal algorithm for floorplan area optimization,” in Proc. Design Automation Conf. 1990, pp. 180–186.
21. T. C. Wang and D. F. Wong, “A Note on the Complexity of Stock-meyer's Floorplan Optimization Technique,” Manuscript, 1991.
22. S. Wimer, I. Koren, and I. Cederbaum, “Optimal aspect ratios of building blocks in VLSI,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 139–145, 1989.
23. D. F. Wong and P. S. Sakhamuri, “Efficient floorplan area optimization,” in Proc. Design Automation Conf., 1989, pp. 586–589.
24. K. H. Yeap and M. Sarrafzadeh, “A theorem of sliceability,” in Proc. Second Great Lakes Comp. Science Conf., October 1991.
25. K. H. Yeap and M. Sarrafzadeh, “Floorplanning by graph dualization: 2-concave rectilinear modules,” SIAM J. Comp., vol. 22, no. 3, pp. 500–526, June 1993.
26. K. H. Yeap and M. Sarrafzadeh, “Sliceable Floorplanning by Graph Dualization.” Manuscript, 1992.