Area Minimization for Floorplans

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 1, 1995, Pages 123-132

  Pan, Peichen ^a   Liu, C L ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; POLYNOMIALS;

FLOORPLAN SIZING PROBLEM;

VLSI CIRCUITS;

EID: 0029220048     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.363119     Document Type: Article

References (15)

1. R. L. Brooks, C. A. B. Smith, A. H. Stone, and W. T. Tutte, “The dissection of rectangles into squares,” Duke Math. J., vol. 7, pp. 312–340, 1940.
2. K. Chong and S. Sahni, “Optimal realizations of floorplans,” IEEE Trans. Computer-Aided Design, vol. 12, no. 6, pp. 793–801, 1993.
3. Wei-Ming Dai and E. S. Kuh, “Simultaneous floor planning and global routing for hierarchical building block layout,” IEEE Trans. Computer-Aided Design, vol. 6, no. 5, pp. 828–837, 1987.
4. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. New York: Wiley, 1990.
5. C. L. Liu, Introduction to Combinatorial Mathematics. New York: McGraw-Hill, 1968.
6. R. H. J. M. Otten, “Automatic floorplan design,” in Proc. 19th ACM/IEEE Design Automat. Conf., 1982, pp. 261–267.
7. R. H. J. M. Otten, “Graphs in floorplan design,” Int. J. Circuit Theory Applic., vol. 16, pp. 391–410, 1988.
8. P. Pan, W. Shi, and C. L. Liu, “Area minimization for hierarchical floorplans,” in Dig. Int. Conf. Computer-Aided Design, to be published.
9. L. Stockmeyer, “Optimal orientations of cells in slicing floorplan designs,” Info. Control, vol. 59, pp. 91–101, 1983.
10. J. Valdes, R. E. Tarjan, and E. L. Lawler, “The recognition of series parallel digraphs,” SIAM J. Comput., vol. 11, no. 2, pp. 298–313, 1982.
11. T.-C. Wang and D. F. Wong, “Optimal floorplan area optimization,” IEEE Trans. Computer-Aided Design, vol. 11, no. 8, pp. 992–1002, 1992.
12. S. Wimer, I. Koren, and I. Cederbaum, “Optimal aspect ratios of building blocks in VLSI,” IEEE Trans. Computer-Aided Design, vol. 8, no 2, pp. 139–145, 1989.
13. D. F. Wong and P. S. Sakhamuri, “Efficient floorplan area optimization,” in Proc. 26th ACM/IEEE Design Automat. Conf., 1989, pp. 586–589.
14. K. H. Yeap and M. Sarrafzadeh, “An integrated algorithm for optimal floorplan sizing and enumeration,” in Euro. Design Automat. Conf., 1993, pp. 29–33.
15. G. Zimmermann, “A new area and shape function estimation technique for VLSI layouts,” in Proc. 25th ACM/IEEE Design Automat. Conf., 1988, pp. 60–65.