Area minimization for hierarchical floorplans

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 436-440

  Pan, Peichen ^a   Shi, Weiping ^a   Liu, C L ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; OPTIMIZATION; POLYNOMIALS; VLSI CIRCUITS;

HIERARCHICAL FLOORPLANS; MINIMIZATION PROBLEM; SET OF REDUNDANT REALIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0028695093     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (16)