Cycle structure of channel graphs in nonslicible floorplans and a unified algorithm for feasible routing order

IEEE International Conference on Computer Design - VLSI in Computers and Processors

Volumn , Issue , 1991, Pages 524-527

  Sur Kolay, Susmita ^a   Bhattacharya, Bhargab B ^a  

^a INDIAN STATISTICAL INSTITUTE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; GRAPH THEORY;

CHANNEL GRAPHS; CHANNEL ROUTING ORDERS; MINIMUM FEEDBACK VERTEX SET; MONOTONE CHANNELS; NONSLICIBLE FLOORPLANS; ROUTING ORDERS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0026263332     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)