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Volumn 8, Issue 2, 1989, Pages 139-145

Optimal Aspect Ratios of Building Blocks in VLSI

Author keywords

area optimization; aspect ratio; branch and bound; Floorplan; layout

Indexed keywords

MATHEMATICAL TECHNIQUES--GRAPH THEORY; OPTIMIZATION;

EID: 0024612408     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.21832     Document Type: Article
Times cited : (28)

References (6)
  • 1
    • 0023146995 scopus 로고
    • Digraph relaxation for 2-dimensional placement of IC blocks
    • Jan.
    • M.J. Ciesielski and E. Kinnen, “Digraph relaxation for 2-dimensional placement of IC blocks,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 55–66, Jan. 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.6 CAD , pp. 55-66
    • Ciesielski, M.J.1    Kinnen, E.2
  • 3
    • 0020746257 scopus 로고
    • Optimal orientations of cells in slicing floorplan designs
    • L. Stockmeyer, “Optimal orientations of cells in slicing floorplan designs,” Inform. Contr., vol. 57, pp. 91–101, 1983.
    • (1983) Inform. Contr. , vol.57 , pp. 91-101
    • Stockmeyer, L.1
  • 4
    • 0001404569 scopus 로고
    • The recognition of series parallel digraphs
    • J. Valdes, R.E. Tarjan, and E.L. Lawler, “The recognition of series parallel digraphs,” SIAM J. Comput., pp. 298–313, 1982.
    • (1982) SIAM J. Comput. , pp. 298-313
    • Valdes, J.1    Tarjan, R.E.2    Lawler, E.L.3
  • 5
    • 0023982903 scopus 로고
    • Floorplans, planar graphs and layouts
    • Mar.
    • S. Wimer, I. Koren, and I. Cederbaum, “Floorplans, planar graphs and layouts,” IEEE Trans. Circuits Syst., vol. 35, pp. 267–278, Mar. 1988.
    • (1988) IEEE Trans. Circuits Syst. , vol.35 , pp. 267-278
    • Wimer, S.1    Koren, I.2    Cederbaum, I.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.