Efficient algorithm and architecture for post-processor in HDTV

IEEE Transactions on Consumer Electronics

Volumn 44, Issue 1, 1998, Pages 16-26

  Lee, Jae Wook ^a   Park, Jeong Woo ^a   Yang, Myung Hoon ^a   Kang, Sungho ^a   Choe, Yoonsik ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA COMPRESSION; DISPLAY DEVICES; IMAGE PROCESSING; SIGNAL PROCESSING; TELEVISION PICTURE QUALITY;

DIGITAL IMAGE SIGNAL PROCESSING; MEMORY SCHEDULING TECHNIQUE; PIPELINED PARALLEL ARCHITECTURE;

HIGH DEFINITION TELEVISION;

EID: 0031997745     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.663726     Document Type: Article

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