-
1
-
-
0018923294
-
Information transfer and area-time tradeoffs for VLSI multiplication
-
H. Abelson and P. Andreae, “Information transfer and area-time tradeoffs for VLSI multiplication,” Commun. Ass. Comput. Mach., vol. 23, no. 1, pp. 20–23, 1980.
-
(1980)
Commun. Ass. Comput. Mach.
, vol.23
, Issue.1
, pp. 20-23
-
-
Abelson, H.1
Andreae, P.2
-
2
-
-
0020843682
-
Transputer does 5 or more MIPS even when not used in parallel
-
Nov. 17
-
I. Barron et al., “Transputer does 5 or more MIPS even when not used in parallel,” Electronics, pp. 109–115, Nov. 17, 1983.
-
(1983)
Electronics
, pp. 109-115
-
-
Barron, I.1
-
4
-
-
84915211389
-
A critique and an appraisal of VLSI models of computation
-
Rockville, MD: Comput. Sci. Press
-
G. Bilardi, M. Pracchi, and F. P. Preparata, “A critique and an appraisal of VLSI models of computation,” in Proc. CMU Conf. VLSI Syst. Corn-put., 1981. Rockville, MD: Comput. Sci. Press, 1981.
-
(1981)
Proc. CMU Conf. VLSI Syst. Corn-put.
-
-
Bilardi, G.1
Pracchi, M.2
Preparata, F.P.3
-
5
-
-
0021541952
-
A smart optical sensor on silicon
-
Dedham, MA: Artech Jan.
-
G. Bishop and H. Fuchs, “A smart optical sensor on silicon,” in Proc. Conf. Advanced Res. VLSI. Jan. 1984. Dedham, MA: Artech, 1984, pp. 65–73.
-
(1984)
Proc. Conf. Advanced Res. VLSI
, pp. 65-73
-
-
Bishop, G.1
Fuchs, H.2
-
6
-
-
84915157242
-
A 200 MOPS systolic processor
-
Soc. Photo-Opt. Instrum. Eng.
-
J. Blackmer, P. Kuekes, and G. Frank, “A 200 MOPS systolic processor,” in Proc. SPIE, vol. 298, Real-Time Signal Processing IV, Soc. Photo-Opt. Instrum. Eng., 1981.
-
(1981)
Proc. SPIE, vol. 298, Real-Time Signal Processing IV
-
-
Blackmer, J.1
Kuekes, P.2
Frank, G.3
-
8
-
-
84909772930
-
Systolic array processor developments
-
Rockville, MD: Comput. Sci. Press Oct.
-
K. Bromley et al., “Systolic array processor developments,” in Proc. CMU Conf. VLSI Syst. Comput., Oct. 1981. Rockville, MD: Comput. Sci. Press, 1981, pp. 273–284.
-
(1981)
Proc. CMU Conf. VLSI Syst. Comput.
, pp. 273-284
-
-
Bromley, K.1
-
9
-
-
0039101652
-
The tree machine: A highly concurrent computing environment
-
Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech Rep Pasadena, Tech Rep. 3760:TR:80
-
S. A. Browning, “The tree machine: A highly concurrent computing environment,” Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech Rep. 3760:TR:80, 1980.
-
(1980)
-
-
Browning, S.A.1
-
11
-
-
84910421933
-
Communication in a tree machine
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
S. A. Browning and C. L. Seitz, “Communication in a tree machine,” in Proc. 2nd Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1981, 509–526.
-
(1981)
Proc. 2nd Caltech Conf. VLSI
, pp. 509-526
-
-
Browning, S.A.1
Seitz, C.L.2
-
12
-
-
11144284284
-
Bit serial inner product processors in VLSI
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
M. R. Buric and C. Mead, “Bit serial inner product processors in VLSI,” in Proc. 2nd Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1981, pp. 155–164.
-
(1981)
Proc. 2nd Caltech Conf. VLSI
, pp. 155-164
-
-
Buric, M.R.1
Mead, C.2
-
13
-
-
0037581100
-
A smart memory array processor for two layer path finding
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
C. R. Carroll, “A smart memory array processor for two layer path finding,” in Proc. 2nd Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1981, pp. 165–195.
-
(1981)
Proc. 2nd Caltech Conf. VLSI
, pp. 165-195
-
-
Carroll, C.R.1
-
14
-
-
2342589171
-
Programming the connection machine
-
M.S. thesis, Dep. Elec. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge
-
D. P. Christman, “Programming the connection machine,” M.S. thesis, Dep. Elec. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, 1984.
-
(1984)
-
-
Christman, D.P.1
-
15
-
-
0017110720
-
Simplified control of FFT hardware
-
Dec.
-
D. Cohen, “Simplified control of FFT hardware,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-24, Dec. 1976.
-
(1976)
IEEE Trans. Acoust., Speech, Signal Processing
, vol.ASSP-24
-
-
Cohen, D.1
-
16
-
-
0018282845
-
Mathematical approach to iterative computation networks
-
Arithmetic (also as ISI/RR-78-73, U.S.C./Inform. Sci. Inst., Marina del Rey, CA, Nov. 1978), IEEE Cat. No. 78CH1412-6C
-
D. Cohen, “Mathematical approach to iterative computation networks,” in Proc. 4th Symp. Comput. Arithmetic (also as ISI/RR-78-73, U.S.C./Inform. Sci. Inst., Marina del Rey, CA, Nov. 1978), IEEE Cat. No. 78CH1412-6C, pp. 226–238, Oct. 1978.
-
(1978)
Proc. 4th Symp. Comput. Arithmetic
, pp. 226-238
-
-
Cohen, D.1
-
17
-
-
0020087077
-
Data flow program graphs
-
Feb.
-
A. L. Davis and R. M. Keller, “Data flow program graphs,” IEEE Computer, vol. 15, pp. 26–41, Feb. 1982.
-
(1982)
IEEE Computer
, vol.15
, pp. 26-41
-
-
Davis, A.L.1
Keller, R.M.2
-
18
-
-
84939701932
-
An introduction to bit-serial architectures for VLSI signal processing
-
Englewood Cliffs, NJ: Prentice-Hall ch. 20.
-
P. B. Denyer, “An introduction to bit-serial architectures for VLSI signal processing,” in VLSI Architecture, B. Randall and P. C. Treieven, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1983, ch. 20.
-
(1983)
VLSI Architecture
-
-
Denyer, P.B.1
Randall, B.2
Treieven, P.C.3
-
19
-
-
0021174294
-
A multiprocessor implementation of relaxation based electrical circuit simulation
-
J. T. Deutch and A. R. Newton, “A multiprocessor implementation of relaxation based electrical circuit simulation,” in Proc. 21st Design Automat. Conf, 1984, pp. 350–357.
-
(1984)
Proc. 21st Design Automat. Conf
, pp. 350-357
-
-
Deutch, J.T.1
Newton, A.R.2
-
20
-
-
0020208486
-
Effects of cache coherency in multiprocessors
-
Nov.
-
M. Dubois and F. A. Briggs, “Effects of cache coherency in multiprocessors,” IEEE Trans. Comput., vol. C-31, Nov. 1982.
-
(1982)
IEEE Trans. Comput.
, vol.C-31
-
-
Dubois, M.1
Briggs, F.A.2
-
21
-
-
0021483148
-
The architecture of a programmable systolic chip
-
A. L. Fisher et al., “The architecture of a programmable systolic chip,” J. VLSI Comput. Syst., vol. 1, no. 2, pp. 1–16, 1984.
-
(1984)
J. VLSI Comput. Syst.
, vol.1
, Issue.2
, pp. 1-16
-
-
Fisher, A.L.1
-
22
-
-
84944998438
-
The use of concurrent processors in science and engineering
-
May
-
G. C. Fox and S. W. Otto, “The use of concurrent processors in science and engineering,” Phys. Today, May 1984.
-
(1984)
Phys. Today
-
-
Fox, G.C.1
Otto, S.W.2
-
23
-
-
0020259174
-
Developing pixel-planes, a smart memory-based raster graphics system
-
Massachusetts Inst. Technol., Cambridge, Jan. 1982. Dedham, MA: Artech
-
H. Fuchs et al., “Developing pixel-planes, a smart memory-based raster graphics system,” in Proc. Conf. Advanced Res. VLSI, Massachusetts Inst. Technol., Cambridge, Jan. 1982. Dedham, MA: Artech, 1982.
-
(1982)
Proc. Conf. Advanced Res. VLSI
-
-
Fuchs, H.1
-
25
-
-
0020283462
-
Systolic networks for orthogonal equivalence transformations and their applications
-
Massachusetts Inst. Technol., Cambridge, Jan. Dedham, MA: Artech
-
D. E. Heller and I. C. F. Ipsen, “Systolic networks for orthogonal equivalence transformations and their applications,” in Proc. Conf. Advanced Res. VLSI, Massachusetts Inst. Technol., Cambridge, Jan. 1982, Dedham, MA: Artech, 1982, pp. 113–122.
-
(1982)
Proc. Conf. Advanced Res. VLSI
, vol.1982
, pp. 113-122
-
-
Heller, D.E.1
Ipsen, I.C.F.2
-
26
-
-
0010842690
-
Encoding knowledge in partitioned networks
-
New York: Academic
-
G. G. Hendrix, “Encoding knowledge in partitioned networks,” in Association Networks. New York: Academic, 1979.
-
(1979)
Association Networks
-
-
Hendrix, G.G.1
-
27
-
-
0021594159
-
VLSI processor architecture
-
this issue
-
J. L. Hennessy, “VLSI processor architecture,” IEEE Trans. Comput., this issue, pp. 1221–1246.
-
IEEE Trans. Comput.
, pp. 1221-1246
-
-
Hennessy, J.L.1
-
28
-
-
84909545464
-
The apiary network architecture for knowledgeable systems
-
Stanford, CA Aug.
-
C. E. Hewitt, “The apiary network architecture for knowledgeable systems,” in Conf. Rec. LISP Conf., Stanford, CA, Aug. 1980.
-
(1980)
Conf. Rec. LISP Conf.
-
-
Hewitt, C.E.1
-
29
-
-
84939353317
-
The connection machine (computer architecture for the new wave)
-
Cambridge, Al Memo 646, Sept.
-
W. D. Hillis, “The connection machine (computer architecture for the new wave),” Massachusetts Inst. Technol., Cambridge, Al Memo 646, Sept. 1981.
-
(1981)
Massachusetts Inst. Technol
-
-
Hillis, W.D.1
-
30
-
-
0018005391
-
Communicating sequential processes
-
C. A. R. Hoare, “Communicating sequential processes,” Commun. Ass. Comput. Mach., vol. 21, no. 8, pp. 666–677, 1978.
-
(1978)
Commun. Ass. Comput. Mach.
, vol.21
, Issue.8
, pp. 666-677
-
-
Hoare, C.A.R.1
-
31
-
-
0000901940
-
Fundamental limitations in microelectronics I, MOS technology
-
B. Hoeneisen and C.A. Mead, “Fundamental limitations in microelectronics I, MOS technology,” Solid-State Electron., vol. 15, pp. 819–829, 1972.
-
(1972)
Solid-State Electron.
, vol.15
, pp. 819-829
-
-
Hoeneisen, B.1
Mead, C.A.2
-
32
-
-
84909707144
-
A mathematical approach to modeling the flow of data and control in computational networks
-
Oct. Rockville, MD: Comput. Sci. Press
-
L. Johnsson and D. Cohen, “A mathematical approach to modeling the flow of data and control in computational networks,” in Proc. CMU Conf. VLSI Syst. Comput., Oct. 1981. Rockville, MD: Comput. Sci. Press, 1981, 213–225.
-
(1981)
Proc. CMU Conf. VLSI Syst. Comput.
, pp. 213-225
-
-
Johnsson, L.1
Cohen, D.2
-
33
-
-
84915207821
-
Computational arrays for band matrix equations
-
Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 4287:TR:81
-
L. Johnsson, “Computational arrays for band matrix equations,” Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 4287:TR:81, 1981.
-
(1981)
-
-
Johnsson, L.1
-
34
-
-
0020305091
-
A computational array for the QR-method
-
Massachusetts Inst. Technol., Cambridge, Dedham, MA: Artech
-
L. Johnsson, “A computational array for the QR-method,” in Proc. Conf. Advanced Res. VLSI, Massachusetts Inst. Technol., Cambridge, 1982. Dedham, MA: Artech, 1982, pp. 123–129.
-
(1982)
Proc. Conf. Advanced Res. VLSI
, pp. 123-129
-
-
Johnsson, L.1
-
35
-
-
3042957955
-
Measurements of parallelism in ordinary FORTRAN programs
-
Jan.
-
D. J. Kuck et al., “Measurements of parallelism in ordinary FORTRAN programs,” IEEE Computer, vol. 7, pp. 37–46, Jan. 1974.
-
(1974)
IEEE Computer
, vol.7
, pp. 37-46
-
-
Kuck, D.J.1
-
38
-
-
0041996562
-
Let’s design algorithms for VLSI
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
H. T. Kung, “Let’s design algorithms for VLSI,” in Proc. Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1979, pp. 65–90.
-
(1979)
Proc. Caltech Conf. VLSI
, pp. 65-90
-
-
Kung, H.T.1
-
39
-
-
0003037829
-
Algorithms for VLSI processor arrays
-
Reading, MA: Addison-Wesley, sect. 8.3
-
H. T. Kung and C. E. Leiserson, “Algorithms for VLSI processor arrays,” in C. A. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, sect. 8.3, pp. 271–292.
-
(1980)
Introduction to VLSI Systems
, pp. 271-292
-
-
Kung, H.T.1
Leiserson, C.E.2
Mead, C.A.3
Conway, L.4
-
40
-
-
0019299804
-
The structure of parallel algorithms
-
New York: Academic
-
H. T. Kung, “The structure of parallel algorithms,” in Advances in Computers, vol. 19. New York: Academic, 1980.
-
(1980)
Advances in Computers
, vol.19
-
-
Kung, H.T.1
-
41
-
-
0019923189
-
Why systolic architectures?
-
Jan.
-
H. T. Kung, “Why systolic architectures?,” IEEE Computer, vol. 15, Jan. 1982.
-
(1982)
IEEE Computer
, vol.15
-
-
Kung, H.T.1
-
42
-
-
0020203229
-
Wavefront array processor: Language, architecture, and applications
-
Nov.
-
S. -Y. Kung et al., “Wavefront array processor: Language, architecture, and applications,” IEEE Trans. Comput., vol. C-31, pp. 1054–1066, Nov. 1982.
-
(1982)
IEEE Trans. Comput.
, vol.C-31
, pp. 1054-1066
-
-
Kunget, S.Y.1
-
43
-
-
1642329047
-
The extension of object-oriented languages to a homogeneous concurrent architecture
-
Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 5014:TR:82
-
C. R. Lang, Jr., “The extension of object-oriented languages to a homogeneous concurrent architecture,” Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 5014:TR:82, 1982.
-
(1982)
-
-
Lang, C.R.1
-
44
-
-
0016624050
-
Access and alignment of data in an array processor
-
Dec.
-
D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Comput., vol. C-24, pp. 1145–1155, Dec. 1975.
-
(1975)
IEEE Trans. Comput.
, vol.C-24
, pp. 1145-1155
-
-
Lawrie, D.H.1
-
45
-
-
84882536619
-
An algorithm for path connections and its applications
-
Sept.
-
C. Lee, “An algorithm for path connections and its applications,” IRE Trans. Electron. Comput., vol. EC-10, pp. 346–365, Sept. 1961.
-
(1961)
IRE Trans. Electron. Comput.
, vol.EC-10
, pp. 346-365
-
-
Lee, C.1
-
46
-
-
84939747068
-
Architecture for VLSI design of Reed-Solomon encoders
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
K. Y. Liu, “Architecture for VLSI design of Reed-Solomon encoders,” in Proc. 2nd Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1981, pp. 539–554.
-
(1981)
Proc. 2nd Caltech Conf. VLSI
, pp. 539-554
-
-
Liu, K.Y.1
-
47
-
-
84939747597
-
The homogeneous machine
-
Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 3759:TR:80
-
B. Locanthi, “The homogeneous machine,” Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 3759:TR:80, 1980.
-
(1980)
-
-
Locanthi, B.1
-
48
-
-
0021540267
-
Design of the mosaic element
-
Massachusetts Inst. Technol., Cambridge, Dedham, MA: Artech
-
C. Lutz et al., “Design of the mosaic element,” in Proc. Conf. Advanced Res. VLSI, Massachusetts Inst. Technol., Cambridge, 1984. Dedham, MA: Artech, 1984, pp. 1–10.
-
(1984)
Proc. Conf. Advanced Res. VLSI
, pp. 1-10
-
-
Lutz, C.1
-
49
-
-
0016945783
-
Two’s complement pipeline multipliers
-
Apr.
-
R. F. Lyon, “Two’s complement pipeline multipliers,” IEEE Trans. Commun., vol. COM-24, pp. 418–425, Apr. 1976.
-
(1976)
IEEE Trans. Commun.
, vol.COM-24
, pp. 418-425
-
-
Lyon, R.F.1
-
50
-
-
0343494553
-
The optical mouse, and an architectural methodology for smart digital sensors
-
Oct. Rockville, MD: Comput. Sci. Press
-
F. Lyon, “The optical mouse, and an architectural methodology for smart digital sensors,” in Proc. CMU Conf. VLSI Syst. Comput., Oct. 1981. Rockville, MD: Comput. Sci. Press, 1981.
-
(1981)
Proc. CMU Conf. VLSI Syst. Comput.
-
-
Lyon, F.1
-
51
-
-
0038457993
-
A bit-serial architectural methodology for signal processing
-
New York: Academic
-
R. F. Lyon, “A bit-serial architectural methodology for signal processing,” in VLSI 81. New York: Academic, 1981.
-
(1981)
VLSI 81
-
-
Lyon, R.F.1
-
52
-
-
30244469668
-
The torus: An exercise in constructing a processing surface
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
A. J. Martin, “The torus: An exercise in constructing a processing surface,” in Proc. 2nd Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1981, pp. 527–538.
-
(1981)
Proc. 2nd Caltech Conf. VLSI
, pp. 527-538
-
-
Martin, A.J.1
-
53
-
-
84944998441
-
A concurrent circuit simulator
-
Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 5142:TR:84
-
S. Mattisson, “A concurrent circuit simulator,” Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 5142:TR:84, 1984.
-
(1984)
-
-
Mattisson, S.1
-
54
-
-
0004263265
-
Introduction to VLSI Systems
-
Reading, MA: Addison-Wesley
-
C. A. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
-
(1980)
-
-
Mead, C.A.1
Conway, L.2
-
55
-
-
0020166761
-
Minimum propagation delays in VLSI
-
Aug.
-
C. A. Mead and M. Rem, “Minimum propagation delays in VLSI,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 773–775, Aug. 1982.
-
(1982)
IEEE J. Solid-State Circuits
, vol.SC-17
, pp. 773-775
-
-
Mead, C.A.1
Rem, M.2
-
56
-
-
0001860685
-
Shortest path through a maze
-
E. Moore, “Shortest path through a maze,” Ann. Comput. Lab. Harvard Univ., vol. 30, pp. 285–292, 1959.
-
(1959)
Ann. Comput. Lab. Harvard Univ.
, vol.30
, pp. 285-292
-
-
Moore, E.1
-
57
-
-
84928336746
-
Are we really ready for VLSI?
-
Dep. Comput. Sci., California Inst. Technol., Pasadena
-
G. E. Moore, “Are we really ready for VLSI?,” in Proc. Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol., Pasadena, 1979.
-
(1979)
Proc. Caltech Conf. VLSI
-
-
Moore, G.E.1
-
58
-
-
0021391524
-
Fifth generation computer systems: A Japanese project
-
Mar.
-
T. Moto-oka and H. S. Stone, “Fifth generation computer systems: A Japanese project,” IEEE Computer, vol. 17, pp. 6–13, Mar. 1984.
-
(1984)
IEEE Computer
, vol.17
, pp. 6-13
-
-
Moto-oka, T.1
Stone, H.S.2
-
59
-
-
0020113493
-
Analysis of multiprocessors with private cache memories
-
Apr.
-
J. H. Patel, “Analysis of multiprocessors with private cache memories,” IEEE Trans. Comput., vol. C-31, pp. 296–304, Apr. 1982.
-
(1982)
IEEE Trans. Comput.
, vol.C-31
, pp. 296-304
-
-
Patel, J.H.1
-
60
-
-
0018982833
-
Design considerations for single-chip computers of the future
-
Feb.
-
D. A. Patterson and C. H. Sequin, “Design considerations for single-chip computers of the future,” IEEE J. Solid-State Circuits, vol. SC-15, Feb. 1980.
-
(1980)
IEEE J. Solid-State Circuits
, vol.SC-15
-
-
Patterson, D.A.1
Sequin, C.H.2
-
61
-
-
0001316941
-
An adaptation of the fast Fourier transform for parallel processing, ” J. Ass
-
M. C. Pease, III, “An adaptation of the fast Fourier transform for parallel processing,” J. Ass. Comput. Mach., vol. 15, pp. 252–264, 1968.
-
(1968)
Comput. Mach.
, vol.15
, pp. 252-264
-
-
Pease, M.C.1
-
62
-
-
0017495099
-
The indirect binary n-cube microprocessor array
-
May
-
M. C. Pease, III, “The indirect binary n-cube microprocessor array,” IEEE Trans. Comput., vol. C-26, pp. 458–473, May 1977.
-
(1977)
IEEE Trans. Comput.
, vol.C-26
, pp. 458-473
-
-
Pease, M.C.1
-
63
-
-
84944998442
-
A mesh-connected area-time optimal VLSI integer multiplier
-
Rockville, MD: Comput. Sci. Press
-
F. P. Preparata, “A mesh-connected area-time optimal VLSI integer multiplier,” in Proc. CMU Conf. VLSI Syst. Comput., 1981. Rockville, MD: Comput. Sci. Press, 1981.
-
(1981)
Proc. CMU Conf. VLSI Syst. Comput.
-
-
Preparata, F.P.1
-
66
-
-
0020280625
-
Ensemble architectures for VLSI — A survey and taxonomy
-
Massachusetts Inst. Technol., Cambridge, Jan. Dedham, MA: Artech
-
C. L. Seitz, “Ensemble architectures for VLSI — A survey and taxonomy,” in Proc. Conf. Advanced Res. VLSI, Massachusetts Inst. Technol., Cambridge, Jan. 1982. Dedham, MA: Artech, 1982, pp. 130–135.
-
(1982)
Proc. Conf. Advanced Res. VLSI
, pp. 130-135
-
-
Seitz, C.L.1
-
67
-
-
0022488602
-
Experiments with VLSI ensemble machines
-
C. L. Seitz, “Experiments with VLSI ensemble machines,” J. VLSI Comput. Syst., vol. 1, no. 3, 1984.
-
(1984)
J. VLSI Comput. Syst.
, vol.1
, Issue.3
-
-
Seitz, C.L.1
-
68
-
-
0021427258
-
Engineering limits on computer performance
-
May
-
C. L. Seitz and J. Matisoo, “Engineering limits on computer performance,” Phys. Today, pp. 38–45, May 1984.
-
(1984)
Phys. Today, pp
, pp. 38-45
-
-
Seitz, C.L.1
Matisoo, J.2
-
70
-
-
0018479403
-
Interconnection networks for SIMD machines
-
June
-
H. J. Siegel, “Interconnection networks for SIMD machines,” IEEE Computer, vol. 12, pp. 57–65, June 1979.
-
(1979)
IEEE Computer
, vol.12
, pp. 57-65
-
-
Siegel, H.J.1
-
71
-
-
0015968264
-
A programmable printed wiring router
-
June
-
C. S. Slemaker, R. C. Mosteller, L. W. Leyking, and A. G. Livitsanos, “A programmable printed wiring router,” in Proc. 11th Design Automat. Workshop, June 1974.
-
(1974)
Proc. 11th Design Automat. Workshop
-
-
Slemaker, C.S.1
Mosteller, R.C.2
Leyking, L.W.3
Livitsanos, A.G.4
-
72
-
-
0019895656
-
Introduction to the configurable highly parallel computer
-
Jan.
-
L. Snyder, “Introduction to the configurable highly parallel computer,” IEEE Computer, vol. 15, pp. 47–56, Jan. 1982.
-
(1982)
IEEE Computer
, vol.15
, pp. 47-56
-
-
Snyder, L.1
-
73
-
-
0015017871
-
Parallel processing with the perfect shuffle
-
H. S. Stone, “Parallel processing with the perfect shuffle,” IEEE Trans. Comput., vol. C-20, 1971.
-
(1971)
IEEE Trans. Comput.
, vol.C-20
-
-
Stone, H.S.1
-
74
-
-
0004924250
-
-
Chicago, IL: Sci. Res. Assoc., particularly
-
H. S. Stone, Ed., Introduction to Computer Architecture. Chicago, IL: Sci. Res. Assoc., 1975, particularly pp. 318–374.
-
(1975)
Introduction to Computer Architecture
, pp. 318-374
-
-
Stone, H.S.1
-
75
-
-
84944998444
-
Super mesh
-
M.S. thesis, Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 5125:TR:84
-
W. -K. Su, “Super mesh,” M.S. thesis, Dep. Comput. Sci., California Inst. Technol., Pasadena, Tech. Rep. 5125:TR:84, 1984.
-
(1984)
, pp. 5125
-
-
Su, W.K.1
-
77
-
-
59049100343
-
Microelectronics and computer science
-
Sept.
-
I. E. Sutherland and C. A. Mead, “Microelectronics and computer science,” Sci. Amer., vol. 237, pp. 210–229, Sept. 1977.
-
(1977)
Sci. Amer.
, vol.237
, pp. 210-229
-
-
Sutherland, I.E.1
Mead, C.A.2
-
78
-
-
0017631734
-
CM* — A modular multimicroprocessor
-
AFIPS Press
-
R.J. Swan et al., “CM* — A modular multimicroprocessor,” in Proc. Nat. Comput. Conf., vol. 46. AFIPS Press, 1977, pp. 637–644.
-
(1977)
Proc. Nat. Comput. Conf.
, vol.46
, pp. 637-644
-
-
Swan, R.J.1
-
79
-
-
0015330654
-
Ion-implanted complementary MOS transistors in low-voltage circuits
-
Apr.
-
R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 146–153, Apr. 1972.
-
(1972)
IEEE J. Solid-State Circuits
, vol.SC-7
, pp. 146-153
-
-
Swanson, R.M.1
Meindl, J.D.2
-
80
-
-
84915200592
-
NOSC systolic processor testbed
-
Tech. Rep. TR NOSC TD 588, June
-
J. J. Symanski. “NOSC systolic processor testbed,” Naval Ocean Syst. Cen., Tech. Rep. TR NOSC TD 588, June 1983.
-
(1983)
Naval Ocean Syst Cen
-
-
Symanski, J.J.1
-
81
-
-
84944982912
-
A VLSI tactile sensing array computer
-
Dep. Comput. Sci., California Inst. Technol. Pasadena, Jan.
-
J. E. Tanner, M. H. Raibert, and R. Eskenazi, “A VLSI tactile sensing array computer,” in Proc. 2nd Caltech Conf. VLSI, Dep. Comput. Sci., California Inst. Technol. Pasadena, Jan. 1981, pp. 217–234.
-
(1981)
Proc. 2nd Caltech Conf. VLSI
, pp. 217-234
-
-
Tanner, J.E.1
Raibert, M.H.2
Eskenazi, R.3
-
82
-
-
0021555064
-
A correlating optical motion detector
-
Massachusetts Inst. Technol., Cambridge, Jan. Dedham, MA: Artech
-
J. E. Tanner and C. Mead, “A correlating optical motion detector,” in Proc. Conf. Advanced Res. VLSI, Massachusetts Inst. Technol., Cambridge, Jan. 1984. Dedham, MA: Artech, 1984, 57–64.
-
(1984)
Proc. Conf. Advanced Res. VLSI
, pp. 57-64
-
-
Tanner, J.E.1
Mead, C.2
-
83
-
-
0004217544
-
A complexity theory for VLSI
-
Dep. Comput. Sci., Camegie-Mellon Univ., Pittsburgh, PA, Tech. Rep. CMU-CS-80-140, Aug.
-
C. D. Thompson, “A complexity theory for VLSI,” Dep. Comput. Sci., Camegie-Mellon Univ., Pittsburgh, PA, Tech. Rep. CMU-CS-80-140, Aug. 1980.
-
(1980)
-
-
Thompson, C.D.1
-
84
-
-
84939707746
-
The VLSI complexity of sorting
-
Computer Science Press, Oct.
-
C. D. Thompson, “The VLSI complexity of sorting,” in Proc. CMC Conf. VLSI Syst. Comput., Computer Science Press, Oct. 1981, pp. 108–118.
-
(1981)
Proc. CMC Conf. VLSI Syst. Comput.
, pp. 108-118
-
-
Thompson, C.D.1
-
85
-
-
0020886345
-
The VLSI complexity of sorting
-
Dec.
-
C. D. Thompson,, “The VLSI complexity of sorting,” IEEE Trans. Comput., vol. C-32, pp. 1171–1184, Dec. 1983.
-
(1983)
IEEE Trans. Comput.
, vol.C-32
, pp. 1171-1184
-
-
Thompson, C.D.1
-
86
-
-
84876638447
-
A wavefront notation tool for VLSI array design
-
Computer Science Press, Oct.
-
U. Weiser and A. Davis, “A wavefront notation tool for VLSI array design,” in Proc. CMC Conf. VLSI Syst. Comput., Computer Science Press, Oct. 1981, pp. 226–234.
-
(1981)
Proc. CMC Conf. VLSI Syst. Comput.
, pp. 226-234
-
-
Weiser, U.1
Davis, A.2
-
87
-
-
33747359216
-
Bit serial Reed-Solomon decoders
-
Ph.D. dissertation, Dep. Comput. Sci., California Inst. Technol., June
-
D. Whiting, “Bit serial Reed-Solomon decoders,” Ph.D. dissertation, Dep. Comput. Sci., California Inst. Technol., June 1984.
-
(1984)
-
-
Whiting, D.1
|