-
1
-
-
0015204214
-
The organization and use of parallel memories
-
P. Budnik and D.J. Kuck, “The organization and use of parallel memories,” IEEE Trans. Computers, vol. 20, no. 12, pp. 1, 566–1, 569, 1971.
-
(1971)
IEEE Trans. Computers
, vol.20
, Issue.12
, pp. 1, 566-1, 569
-
-
Budnik, P.1
Kuck, D.J.2
-
2
-
-
0024667387
-
Analysis of vector access performance on skewed interleaved memory
-
C-L. Chen and C-K Liao, “Analysis of vector access performance on skewed interleaved memory,” Int'l Symp. Computer Architecture, pp. 387–394, 1989.
-
(1989)
Int'l Symp. Computer Architecture
, pp. 387-394
-
-
Chen, C.-L.1
Liao, C.-K.2
-
3
-
-
0022242041
-
XOR-schemes: A flexible data organization in parallel memories
-
J. Frailong, W. Jalby, and J. Lenfant, “XOR-schemes: A flexible data organization in parallel memories,” Int'l Conf. Parallel Processing, pp. 276–283, 1985.
-
(1985)
Int'l Conf. Parallel Processing
, pp. 276-283
-
-
Frailong, J.1
Jalby, W.2
Lenfant, J.3
-
4
-
-
0026157234
-
Data prefetching in multiprocessor vector cache memories
-
J.W.C. Fu and J.H. Patel: “Data prefetching in multiprocessor vector cache memories,” Int'l Symp. Computer Architecture, pp. 54–63, 1991.
-
(1991)
Int'l Symp. Computer Architecture
, pp. 54-63
-
-
Fu, J.W.C.1
Patel, J.H.2
-
5
-
-
0022583629
-
Performance evaluation of vector accesses in parallel memories using a skewed storage scheme
-
D.T. Harper III and JR. Jump, “Performance evaluation of vector accesses in parallel memories using a skewed storage scheme,” Int'l Symp. Computer Architecture, pp. 324–328, 1986.
-
(1986)
Int'l Symp. Computer Architecture
, pp. 324-328
-
-
Harper, D.T.1
Jump, J.2
-
6
-
-
0025782109
-
Block, multistride vector and FFT accesses in parallel memory systems
-
D.T. Harper III, “Block, multistride vector and FFT accesses in parallel memory systems,” IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 1, pp. 43–51, 1991.
-
(1991)
IEEE Trans. Parallel and Distributed Systems
, vol.2
, Issue.1
, pp. 43-51
-
-
Harper, D.T.1
-
8
-
-
0026122803
-
Conflict-free vector access using a dynamic storage scheme
-
D.T. Harper III and DA. Linebarger, “Conflict-free vector access using a dynamic storage scheme,” IEEE Trans. Computers, vol. 40, no. 3, pp. 276–283, 1991.
-
(1991)
IEEE Trans. Computers
, vol.40
, Issue.3
, pp. 276-283
-
-
Harper, D.T.1
Linebarger, D.A.2
-
9
-
-
0016624050
-
Access and alignment of data in an array processor
-
Dec.
-
D.H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Computers, vol. 24, no. 12, pp. 1, 145–1, 155, Dec. 1975.
-
(1975)
IEEE Trans. Computers
, vol.24
, Issue.12
, pp. 1, 145-1, 155
-
-
Lawrie, D.H.1
-
10
-
-
0023565195
-
A class of boolean linear transformations for conflict-free power-of-two stride access
-
A. Norton and E. Melton, “A class of boolean linear transformations for conflict-free power-of-two stride access,” Int'l Conf. Parallel Processing, pp. 247–254, 1987.
-
(1987)
Int'l Conf. Parallel Processing
, pp. 247-254
-
-
Norton, A.1
Melton, E.2
-
11
-
-
0022138619
-
On the effective bandwidth of interleaved memories in vector processing systems
-
Oct.
-
W. Oed and O. Lange, “On the effective bandwidth of interleaved memories in vector processing systems,” IEEE Trans. Computers, vol. 34, no. 10, pp. 949–957, Oct. 1985.
-
(1985)
IEEE Trans. Computers
, vol.34
, Issue.10
, pp. 949-957
-
-
Oed, W.1
Lange, O.2
-
12
-
-
0024927072
-
The Cydra∡ 5 stride-insensitive memory system
-
B.R. Rau, M.S. Schlansker, and D.W.L. Yen, “The Cydra∡ 5 stride-insensitive memory system,” Int'l Conf. Parallel Processing, pp. 242–246, 1989.
-
(1989)
Int'l Conf. Parallel Processing
, pp. 242-246
-
-
Rau, B.R.1
Schlansker, M.S.2
Yen, D.W.L.3
-
14
-
-
85026948113
-
Conflict-free access of vectors with power-of-two strides
-
M. Valero, T. Lang, and E. Ayguade, “Conflict-free access of vectors with power-of-two strides,” Int'l Conf Supercomputing, pp. 149–156, 1992.
-
(1992)
Int'l Conf Supercomputing
, pp. 149-156
-
-
Valero, M.1
Lang, T.2
Ayguade, E.3
-
15
-
-
0026865523
-
Increasing the number of strides for conflict-free vector access
-
M. Valero, T. Lang, J.M. Llaberia, M. Peiron, E. Ayguade, and J.J. Navarro: “Increasing the number of strides for conflict-free vector access,” Int'l Symp. Computer Architecture, pp. 372–381, 1992.
-
(1992)
Int'l Symp. Computer Architecture
, pp. 372-381
-
-
Valero, M.1
Lang, T.2
Llaberia, J.M.3
Peiron, M.4
Ayguade, E.5
Navarro, J.J.6
-
16
-
-
0024666942
-
An aperiodic storage scheme to reduce memory conflicts in vector processors
-
S. Weiss, “An aperiodic storage scheme to reduce memory conflicts in vector processors,” Int'l Symp. Computer Architecture, pp. 380–386, 1989.
-
(1989)
Int'l Symp. Computer Architecture
, pp. 380-386
-
-
Weiss, S.1
-
17
-
-
0022083698
-
The structure of periodic storage schemes for parallel memories
-
June
-
H.A.G. Wijshoff and J. van Leeuwen, “The structure of periodic storage schemes for parallel memories,” IEEE Trans. Computers, vol. 34, pp. 501–505, June 1985.
-
(1985)
IEEE Trans. Computers
, vol.34
, pp. 501-505
-
-
Wijshoff, H.A.G.1
van Leeuwen, J.2
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