An efficient pipelined parallel architecture for blocking effect removal in hdtv

IEEE Transactions on Consumer Electronics

Volumn 43, Issue 2, 1997, Pages 149-156

  Lee, Jae Wook ^a   Yang, Myung Hoon ^a   Kang, Sungho ^a   Choe, Yoonsik ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; TELEVISION PICTURE QUALITY;

BLOCKING EFFECTS; PIPELINE PARALLEL ARCHITECTURE;

HIGH DEFINITION TELEVISION;

EID: 0031145966     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.585533     Document Type: Article

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