A Single Chip Video Signal Processing Architecture for Image Processing, Coding, and Computer Vision

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 5, Issue 5, 1995, Pages 436-445

  Goodenough, John ^a   Meacham, Richard J ^a   Morris, Jonathan D ^a   Seed, N Luke ^a   Ivey, Peter A ^a  

^a UNIVERSITY OF SHEFFIELD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER VISION; IMAGE CODING; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTING SILICON; STANDARDS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

ARCHITECTURAL FLEXIBILITY; ARRAY CORE ARCHITECTURE; DATAPATH; INTELLIGENT MEMORY INTERFACE PROCESSOR; SINGLE CHIP VIDEO SIGNAL PROCESSING; VIDEO SIGNAL PROCESSOR;

MICROPROCESSOR CHIPS;

EID: 0029386681     PISSN: 10518215     EISSN: 15582205     Source Type: Journal    
DOI: 10.1109/76.473556     Document Type: Article

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