Evaluation of Booth encoding techniques for parallel multiplier implementation

Electronics Letters

Volumn 29, Issue 23, 1993, Pages 2016-2017

  Villeger, D ^a   Oklobdzija, V G ^b  

^a ESYCOM   (France)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital arithmetic; Multipliers

Indexed keywords

ALGORITHMS; DATA COMPRESSION; DATA REDUCTION; DIGITAL ARITHMETIC; ERROR CORRECTION; MULTIPLYING CIRCUITS; TREES (MATHEMATICS);

BOOTH ENCODING TECHNIQUES; BOOTH MACSORLEY RECODING; PARALLEL MULTIPLIER IMPLEMENTATION;

ENCODING (SYMBOLS);

EID: 0027694803     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19931345     Document Type: Article

References (5)

1. BOOTH, A.D.: ‘A signed binary multiplication technique’, Quarterly J. Meehan. Appl. Math., 1951, IV
2. MACSORLEY, O.L.: ‘High speed arithmetic in binary computers’, Proc. IRE, 1961, 49, (1)
3. WEINBERGER, A.: ‘4:2 carry-save adder module’, IBM Tech. Disclosure Bulletin, 1981, 23
4. MORI et al., J.: ‘A 10ns 54 x 54-b parallel structured full array multiplier with 0.5-u CMOS technology’, IEEE J. Solid State Circuits, 1991, 26, (4)
5. SOULAS, T., VILLEGER, D., and OKLOBDZIJA, V.G.: ‘An ASIC multiplier for complex numbers’. Proc. EURO-ASIC-93, 22-25 February 1993, (Paris, France)