Node-covering based defect and fault tolerance methods for increased yield in FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 225-229

  Hanchek, Fran ^a   Dutt, Shantanu ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; COMBINATORIAL CIRCUITS; ELECTRIC WIRING; ERROR DETECTION; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC DESIGN; RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER);

FAULT TOLERANCE METHODS; FIELD PROGRAMMABLE GATE ARRAYS; NODE COVERING DEFECT; RECONFIGURABILITY; ROUTING DISCIPLINE; STATIC RANDOM ACCESS MEMORY;

LOGIC GATES;

EID: 0029713590     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)