Design methodologies for tolerating cell and interconnect faults in FPGAs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 326-331

  Hanchek, Fran ^a   Dutt, Shantanu ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; ELECTRIC WIRING; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; MICROPROCESSOR CHIPS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC CELLS; WIRING FAULTS;

CELLULAR ARRAYS;

EID: 0030399709     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)