Rapid thermal annealing on the characteristics of polysilicon thin-film transistors in practical tft sram process

IEEE Transactions on Electron Devices

Volumn 44, Issue 9, 1997, Pages 1561-1562

  Lee, Kan Yuan ^a   Fang, Yean Kuen ^a   Chen, Chii Wen ^a   Liang, Mong Song ^a   Wuu, Shou Gwo ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CURRENT VOLTAGE CHARACTERISTICS; DEGRADATION; DETERIORATION; GATES (TRANSISTOR); LOW TEMPERATURE OPERATIONS; TRANSCONDUCTANCE;

LOW TEMPERATURE ANNEALING;

THIN FILM TRANSISTORS;

EID: 0031233974     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.622618     Document Type: Article

References (6)

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3. H. N. Chern, C. L. Lee, and T. F. Lei, "Correlation of polysilicon thin-film transistor characteristics to defects states via thermal annealing," IEEE Trans. Electron Devices, vol. 41, p. 460, Mar. 1994.
4. J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banerjee, "Anomalous leakage current in LPCVD polysilicon MOSFET's," IEEE Trans. Electron Devices, vol. ED-32, p. 1878, Sept. 1985.
5. M. Bonnel, N. Duhamel, L. Haji, B. Loisel, and J. Stoememos, "Polycrystalline silicon thin-film transistors with two-step annealing process," IEEE Electron Device Lett., vol. 14, p. 551, Dec. 1993.
6. S. J. Krause, B. L. Chen, and M. K. El-Ghor, "Effect of rapid thermal plus conventional annealing on the microstructure of oxygen implanted SOI material," in Proc. IEEE Int. SOI Conf., 1991, p. 114.