Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic

IEE Proceedings: Circuits, Devices and Systems

Volumn 143, Issue 6, 1996, Pages 331-366

  Hanyu, T ^a   Mochizuki, A ^a   Kameyama, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Differential logic; Integrated circuits

Indexed keywords

ADDERS; DELAY CIRCUITS; DETECTOR CIRCUITS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT;

DIFFERENTIAL LOGIC; DUAL RAIL COMPLEMENTARY INPUTS; MULTIPLE CURRENT MODE LOGIC CIRCUITS;

LOGIC CIRCUITS;

EID: 0030392601     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19960710     Document Type: Article

References (11)

1. WATTS, R.K. (Ed.): 'Submicron inteerated circuits' (Wiley Interscience, 1989)
2. HANYU, T., KAMEYAMA, M., and HIGUCHI, T.: 'Prospects of multiple-valued VLSI processors', IEICE Trans. Electron.. 1993, E76-C, (3), pp. 383-392
3. SMITH, K.C.: 'The prospects for multivalued logic: A technology and applications view', IEEE Trans. Comput., 1981, C-30, (9), pp. 619-634
4. HIGUCHI, T., and KAMEYAMA, M.: 'Multiple-valued digital processing system' (Shokodo Co. Ltd., 1989)
5. KAMEYAMA, M., KAWAHITO, S., and HIGUCHI, T.: 'A multiplier chip with multiple-valued bidirectional current-mode logic circuits', Computer, 1988, 21, pp. 43-56
6. HANYU, T., KAMEYAMA, M., and HIGUCHI, T.: 'Beyondbinary circuits for signal processing'. ISSCC Dig. Tech. Pap., 1993, pp. 134-135
7. YAMASHINA, M., and YAMADA, H.: 'An MOS current mode logic (MCML) circuit for low-power sub-GHZ processors', IEICE Trans. Electron., 1992, E-75, (10), pp. 1181-1187
8. HANYU, T., MOCHIZUKI, A., and KAMEYAMA, M.: 'A 200MHz pipelined multiplier using 1.5V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic', IEEEJ. Solid-State Circuits, 1995, 30, (11), pp. 1239-1245
9. AVIZIENIS, A.: 'Signed-digit number representations for fast parallel arithmetic', IRE Trans. Electron. Comput., 1961, 10, (3), pp.389-400
10. KAWAHITO, S., KAMEYAMA, M., and HIGUCHI, T.: 'Multiple-valued radix-2 signed-digit arithmetic circuits for hieh-performance VLSI systems', IEEE J. Solid-States Circuits, 1990, 25, (1), pp. 125-131
11. MAKING, H., NAKASE, Y., and SHINOHARA, H.: 'An 8.8ns 54 x 54-bit multiplier using new redundant binary architecture'. IEEE Proc. Int. Conf. Computer design, 1993, pp. 202-205