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Volumn 21, Issue 4, 1988, Pages 43-56

A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY - MANY VALUED LOGICS; INTEGRATED CIRCUITS, VLSI; LOGIC CIRCUITS; SEMICONDUCTOR DEVICES, MOS;

EID: 0023997332     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.50     Document Type: Article
Times cited : (61)

References (12)
  • 1
    • 0023166891 scopus 로고
    • A High-Speed Compact Multiplier Based on Multiple-Valued Bi-Directional Current-Mode Circuits
    • May
    • S. Kawahito et al., “A High-Speed Compact Multiplier Based on Multiple-Valued Bi-Directional Current-Mode Circuits,” Proc.1987 Int’l Symp. Multiple-Valued Logic, May 1987, pp. 172–180.
    • (1987) Proc.1987 Int’l Symp. Multiple-Valued Logic , pp. 172-180
    • Kawahito, S.1
  • 2
    • 0021609266 scopus 로고    scopus 로고
    • Multiple-Valued Logic—Its Status and Its Future
    • Dec.
    • S.L. Hurst,’’Multiple-Valued Logic—Its Status and Its Future,” IEEE Trans. Computers, Dec. 1984, pp. 1160–1179.
    • IEEE Trans. Computers , pp. 1160-1179
    • Hurst, S.L.1
  • 4
    • 0018983901 scopus 로고
    • High Density Integrated Computing Circuitry with Multiple-Valued Logic
    • Feb.
    • K.W. Current, “High Density Integrated Computing Circuitry with Multiple-Valued Logic,” IEEE J. Solid-State Circuits, Feb. 1980, pp. 127–131.
    • (1980) IEEE J. Solid-State Circuits , pp. 127-131
    • Current, K.W.1
  • 5
    • 0023293386 scopus 로고
    • Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing
    • Feb.
    • M. Kameyama, T. Hanyu, and T.Higuchi, “Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing,” IEEE J. Solid-State Circuits, Feb. 1987, pp. 20–27.
    • (1987) IEEE J. Solid-State Circuits , pp. 20-27
    • Kameyama, M.1    Hanyu, T.2    Higuchi, T.3
  • 6
    • 84937078021 scopus 로고
    • Signed-Digit Number Representations for Fast Parallel Arithmetic
    • Sept.
    • A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Elect. Computing, Sept. 1961, pp. 389–400.
    • (1961) IRE Trans. Elect. Computing , pp. 389-400
    • Avizienis, A.1
  • 7
    • 67649098877 scopus 로고
    • Residue Number System Arithmetic: Modern Applications in Digital Signal Processing
    • New York
    • M.A. Soderstrand et al., eds., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, New York, 1986.
    • (1986) IEEE Press
    • Soderstrand, M.A.1
  • 8
    • 84944981017 scopus 로고    scopus 로고
    • A Proof of the Modified Booth’s Algorithm for Multiplication
    • Oct.
    • L.P. Rubinfield, “A Proof of the Modified Booth’s Algorithm for Multiplication,” IEEE Trans. Computers, Oct. 1975, pp. 1014–1015.
    • IEEE Trans. Computers , pp. 1014-1015
    • Rubinfield, L.P.1
  • 9
    • 0022563540 scopus 로고
    • VLSI-Oriented Bi-Directional Current-Mode Arithmetic Circuits Based on the Radix-4 Signed-Digit Number System
    • May
    • S. Kawahito, M. Kameyama, and T. Higuchi, “VLSI-Oriented Bi-Directional Current-Mode Arithmetic Circuits Based on the Radix-4 Signed-Digit Number System,” Proc. 1986 Int’l Symp. Multiple-Valued Logic, May 1986, pp. 70–77.
    • (1986) Proc. 1986 Int’l Symp. Multiple-Valued Logic , pp. 70-77
    • Kawahito, S.1    Kameyama, M.2    Higuchi, T.3
  • 10
    • 0019181801 scopus 로고
    • Design of Radix-4 Signed-Digit Arithmetic Circuits for Digital Filtering
    • June
    • M. Kameyama and T. Higuchi, “Design of Radix-4 Signed-Digit Arithmetic Circuits for Digital Filtering,” Proc. 1980 Int’l Symp. Multiple-Valued Logic, June 1980, pp. 272–277.
    • (1980) Proc. 1980 Int’l Symp. Multiple-Valued Logic , pp. 272-277
    • Kameyama, M.1    Higuchi, T.2
  • 12
    • 84937994302 scopus 로고
    • Diffusion Self-Aligned Enhance-Depletion MOS-IC (DSA-MOS-IC)
    • T. Tarui et al., “Diffusion Self-Aligned Enhance-Depletion MOS-IC (DSA-MOS-IC),” Proc. 2nd Conf. on Solid-State Devices, 1970, p. 193.
    • (1970) Proc. 2nd Conf. on Solid-State Devices , pp. 193
    • Tarui, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.