Greedy Hardware Optimization for Linear Digital Circuits Using Number Splitting and Refactorization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 4, 1993, Pages 423-431

  Chatterjee, Abhijit ^a   Roy, Rabindra K ^b   d'Abreu, Manuel A ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b C&C Research Laboratories NEC USA Inc ^*  (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; PROGRAM COMPILERS; RECURSIVE FUNCTIONS;

DATA FLOW TRANSFORMATION TECHNIQUES; GREEDY HARDWARE OPTIMIZATION; LINEAR DIGITAL CIRCUITS; NUMBER SPLITTING; REFACTORIZATION;

DIGITAL CIRCUITS;

EID: 0027852146     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.250189     Document Type: Article

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