Multiplier blocks and complexity of IIR structures

Electronics Letters

Volumn 30, Issue 22, 1994, Pages 1841-1842

  Dempster, A G ^a   Macleod, M D ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Digital filters; Multiplying circuits

Indexed keywords

ADDERS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK TOPOLOGY; GRAPHIC METHODS; MULTIPLYING CIRCUITS;

MULTIPLIER BLOCKS; WORDLENGTHS;

DIGITAL FILTERS;

EID: 0028526552     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19941288     Document Type: Article

References (12)

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11. DEMPSTER, A.G., and MACLEOD, M.D.: ‘Use of multiplier blocks to reduce filter complexity’. ISCAS 94, April/May 19941994, (IEEE)
12. BULL, D.R., and HORROCKS, D.H.: ‘Realisation techniques for primitive operator infinite impulse response digital filters’. ISCAS 93, 1993, (IEEE), pp. 607–610