A High-Performance 0.25-μm CMOS Technology: II—Technology

IEEE Transactions on Electron Devices

Volumn 39, Issue 4, 1992, Pages 967-975

  Davari, Bijan ^a   Chang, Wen Hsing ^a   Petrillo, K E ^a   Wong, C Y ^a   Moy, Dan ^a   Taur, Yuan ^a   Wordeman, Matthew R ^a   Sun, Jack Yuan Chen ^a   Hsu, Charles Ching Hsiang ^a   Polcari, Michael R ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LITHOGRAPHY; LOGIC DEVICES--GATES; PROCESS CONTROL; SEMICONDUCTOR DEVICES--JUNCTIONS; TECHNOLOGY;

TITANIUM SILICIDE;

INTEGRATED CIRCUITS, CMOS;

EID: 0026852625     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.127490     Document Type: Article

References (24)

1. R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, no. 5, Oct. 1974.
2. B. Davari et al., “A high performance 0.25 μm CMOS technology,” in IEDM Tech. Dig., 1988, p. 56.
3. H. I. Hanafi et al., “0.5 μm CMOS device design and characterization,” in Proc. ESSDERC'87 (Bologna, Italy), p. 21.
4. W. Chang et al., “A high-performance 0.25-μm CMOS technology: I—Design and characterization,” this issue, pp. 959–966.
5. K. Tanaka et al., “Design methodology for deep submicron CMOS,” in IEDM Tech. Dig., 1987, p. 628.
6. B. Davari et al., “Submicron tungsten gate MOSFET'S with 10 nm gate oxide,” in Proc. 1987 Symp. on VLSI Technology (Karuizawa, Japan), p. 61.
7. K. K. Ng et al., “The impact of intrinsic series resistance on MOSFET scaling” in Proc. 1987 Symp. on VLSI Technology (Karuizawa, Japan), p. 503.
8. D. Moy et al., “Use of thin TiSi2 for submicron VLSI CMOS,” in Proc. 1st Int. Symp. on VLSI Science and Technology, ECS, vol. 87–11, 1987, p. 381.
9. K. E. Petrillo et al., “CEL resist processing for submicron CMOS and bipolar circuits,” Adv. Resist Tech, and Proc. V, Proc. SPIE, vol. 920, 1988.
10. J. Y. C. Sun et al., “Study of boron penetration through thin oxide with p + polsilicon gate,” in Proc. 1989 Symp. on VLSI Technology (Kyoto, Japan), p. 17.
11. F. H. Gaensslen et al., “Very small MOSFET's for low temperature operation,” IEEE Trans. Electron Devices, vol. ED-24, p. 218, 1978.
12. C. Y. Wong et al., “Doping of n+ and p+ polysilicon in a dual-gate CMOS process,” in IEDM Tech. Dig., 1988, p. 238.
13. R. A. Chapman et al., “0.5 micron CMOS for high performance at 3.3 V,” in IEDM Tech. Dig., 1988, p. 52.
14. C. C.-H. Hsu et al., “A comparative study of hot-carrier instability in p- and n-type poly gate MOSFETs,” in IEDM Tech. Dig., 1989, p. 75.
15. C. T. Sah et al., “Oxide traps on oxidized silicon,” in Data Rev. Ser. 4, Properties of Silicon, INSPEC, IEE, 1988, pp. 532–547.
16. S. J. Hillenius et al., “A symmetric submicron CMOS technology,” in IEDM Tech. Dig., 1986, p. 52.
17. B. Davari et al., “Very shallow junctions for submicron CMOS technology using implanted Ti for salicidation,” VLSI Sci. Tech. Dig., p. 368, 1987.
18. Y. Taur et al., “Source-drain contact resistance in CMOS with self-aligned TiSi2,” IEEE Trans. Electron Devices, vol. ED-34, no. 3, p. 575, 1987.
19. C. Y. Ting et al., “The use of TiSi2 in a selfaligned silicide technology,” VLSI Sci. Tech. Dig., p. 254, 1982.
20. H. K. Park et al., “Effects of ion implantation doping on the formation of TiSi2,” J. Vac. Sci. Technol. A2, p. 264, 1984.
21. S. Basavaiah et al., “Substrate and dopant effects on the formation of TiSi2,” Proc. Mat. Res. Soc. (Boston, MA), 1986.
22. Y. Koh et al., “Self-aligned TiSi2 for bipolar applications,” J. Vac, Sci. Technol. B, vol. 3, p. 1715, 1985.
23. K. L. Wang et al., “Refractory metal silicide formation by ion implantation,” Thin Solid Films, vol. 74, p. 239, 1980.
24. C. Chang et al., “Corner-field induced drain leakage in thin oxide MOSFETS,” in IEDM Tech. Dig., p. 714, 1987.