Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

International Reliability Workshop Final Report

Volumn , Issue , 1994, Pages 124-128

  Ker, Ming Dou ^a   Wu, Chung Yu ^a   Cheng, Tao ^a   Wu, Michael J N ^a   Yu, T L ^a   Wang, Alex C ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTRIC FAULT CURRENTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OXIDES; PROTECTION; ULSI CIRCUITS; VLSI CIRCUITS;

ELECTROSTATIC DISCHARGE; GATE OXIDE; POWER PINS;

CMOS INTEGRATED CIRCUITS;

EID: 0028736733     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)