Roadmap of CAD tool changes for sub-micron interconnect problems

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 1997, Pages 104-109

  Scheffer, Lou ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NOISE MARGIN; SUB MICRON CHIPS;

ELECTROMIGRATION; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; SPURIOUS SIGNAL NOISE;

COMPUTER AIDED DESIGN;

EID: 0030645043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)