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Volumn 47, Issue 12, 2000, Pages 2385-2391

Power Si-MOSFET operating with high efficiency under low supply voltage

Author keywords

Cosi2 high power added efficiency; Power Si device; Telecommunication IC

Indexed keywords


EID: 0006572417     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.887026     Document Type: Article
Times cited : (6)

References (12)
  • 8
    • 0023995279 scopus 로고    scopus 로고
    • "Deep-submicrometer MOS device fabrication using a photoresist-ashing technique," IEEE Electron Device Lett., vol. 9, pp. 186-188, 1988.
    • J. Chung et al., "Deep-submicrometer MOS device fabrication using a photoresist-ashing technique," IEEE Electron Device Lett., vol. 9, pp. 186-188, 1988.
    • Chung, J.1
  • 9
    • 0027878002 scopus 로고    scopus 로고
    • 50 nm gate length n-MOSFET's with 10 nm phosphorus source and drain junctions," in IEDM Tech. Dig., 1993, pp. 119-122.
    • M. Ono et al, "Sub50 nm gate length n-MOSFET's with 10 nm phosphorus source and drain junctions," in IEDM Tech. Dig., 1993, pp. 119-122.
    • "Sub
    • Ono, M.1
  • 10
    • 0027889412 scopus 로고    scopus 로고
    • et at., 21 ps switching 0.1 μm-CMOS at room temperature using high-performance Co salicide process," in IEDM Tech. Dig., 1993, pp. 906-907.
    • T. Yamazaki et at., "21 ps switching 0.1 μm-CMOS at room temperature using high-performance Co salicide process," in IEDM Tech. Dig., 1993, pp. 906-907.
    • "
    • Yamazaki, T.1
  • 11
    • 0029715056 scopus 로고    scopus 로고
    • et at., 0.15 μm single-gate Co-salicide CMOS," in Symp. VLSI Tech. Dig., 1996, pp. 34-35.
    • T. Yoshitomi et at., "High-performance 0.15 μm single-gate Co-salicide CMOS," in Symp. VLSI Tech. Dig., 1996, pp. 34-35.
    • "High-performance
    • Yoshitomi, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.