On the origin of the dispersion of erased threshold voltages in flash EEPROM memory cells

IEEE Transactions on Electron Devices

Volumn 47, Issue 5, 2000, Pages 1120-1123

  Esseni, David ^a   Riccö, Bruno ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Erasing operation; Flash EEPROM; Thresholds dispersion; Tunneling currents dispersion

Indexed keywords

EID: 0000906920     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.841251     Document Type: Article

References (11)

1. K. Yoshikawa et al, "Comparison of current flash EEPROM erasing methods: Stability and how to control," in IEDM Tech. Dig., 1992, pp. 595-598.
2. A. Bergemont, M. Chi, and H. Haggag, "Low voltage NVG TM: A new high performance 3V/5V flash technology for portable computing and telecommunications applications," IEEE Trans. Electron Devices, vol. 43, pp. 1510-1517, Sept. 1996.
3. B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, "Multi-level flash cells and their trade-offs," in IEDM Tech. Dig., 1996, pp. 169-172.
4. M. Chi, H. Haggag, and A. Bergemont, "A new erase VT distribution model for reliability design in high density flash EEPROM," in Proc. Symp. VLSI Technology, Systems, and Applications, 1995, p. 171.
5. C.-Y. Wu and C.-F. Chen, "Physical model for characterizating and simulating a FLOTOX EEPROM device," Solid-State Electron., vol. 35, no. 5, pp. 705-716, 1992.
6. R.M. Anderson and D. R. Kerr, "Evidence for surface asperity mechanisms of conductivity in oxide grown on polycristalline silicon," J. Appl. Phys., vol. 48, no. 11, pp. 4834-4836, 1977.
7. Y. Hokari, "Stress voltage polarity dependence of thermally grown thin gate oxide wearout," IEEE Trans. Electron Devices, vol. 35, pp. 1299-1304, 1988.
8. 2 films on n+ polycrystalline silicon: Electrical conduction and breakdown," IEEE Trans. Electron Devices, vol. ED-33, pp. 1785-1794, Nov. 1986.
9. R. Turkman, "Electrical characterization of polysilicon surface roughness in double polysilicon EPROMS," in IEDM Tech. Dig., 1991, pp. 79-83.
10. M. Ushiyama étal, "Two dimensional inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory," in Proc. Int. Reliability Physics Symp., 1991, pp. 331-336.
11. S. Muramatsu et al, "The solution of over-erase problem controlling poly-si grain size-Modified scaling principles for FLASH memory," in IEDM Tech. Dig., 1994, pp. 847-850.