Physical model for characterizing and simulating a FLOTOX EEPROM device

Solid State Electronics

Volumn 35, Issue 5, 1992, Pages 705-716

  Wu, Ching Yuan ^a   Chen, Chiou Feng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DATA STORAGE, SEMICONDUCTOR;

EEPROM DEVICES; FLOTOX EEPROM;

DATA STORAGE, DIGITAL;

EID: 0026868413     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(92)90041-A     Document Type: Article

References (22)

1. IEEE Int. Solid-St. Circ. Conf.
2. A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features
3. A high-density, high-performance EEPROM cell
4. IEEE Int. Electron Device Meet. Tech. Dig.
5. Charge retention of floating-gate transistors under applied bias conditions
6. A model for conduction in floating-gate EEPROM's
7. Analysis and modeling of floating-gate EEPROM cells
8. A characterization model for ramp-voltage-stressed I-V characteristics of thin thermal oxides grown on silicon substrate
9. Electrical breakdown in thin gate and tunneling oxides
10. 2films thermally grown on a heavily doped Si substrate—characterization and modeling
11. Implementation of optical interconnections for VLSI